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| 101 innovation drive san jose, ca 95134 www.altera.com siv5v1-4.6 volume 1 stratix iv device handbook
? 2012 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix word s and logos are trademarks of alte ra corporation and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specificat ions in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no respon sibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. september 2012 altera corporation stratix iv device handbook volume 1 iso 9001:2008 registered september 2012 altera corporation stratix iv device handbook volume 1 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi section i. device core chapter 1. overview for the stratix iv device family feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 stratix iv gx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?3 stratix iv e device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?4 stratix iv gt devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?5 architecture features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?6 high-speed transceiver features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?6 highest aggregate data bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?6 wide range of protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?6 diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?7 signal integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?7 fpga fabric and i/o features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 device core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 digital signal processing (dsp) blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?9 i/o features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?9 high-speed differential i/o with dpa and soft-cdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?9 external memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?9 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?10 integrated software platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 chapter 2. logic array blocks and adaptive logic modules in stratix iv devices logic array blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 lab interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 lab control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 adaptive logic modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 alm operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?9 extended lut mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 arithmetic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?12 shared arithmetic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 lut-register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 register chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?17 alm interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 clear and preset logic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 lab power management techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?19 chapter 3. trimatrix embedded memory blocks in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 trimatrix memory block types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 parity bit support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 iv contents stratix iv device handbook september 2012 altera corporation volume 1 byte enable support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 packed mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 address clock enable support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6 mixed width support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7 asynchronous clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7 error correction code (ecc) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8 memory modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9 single-port ram mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10 simple dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?11 true dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?14 shift-register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?16 rom mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17 clocking modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17 independent clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 input/output clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 read/write clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 single clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 selecting trimatrix memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 conflict resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?19 read-during-write behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?19 same-port read-during-write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?19 mixed-port read-during-write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?21 power-up conditions and memory initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?23 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?24 chapter 4. dsp blocks in stratix iv devices stratix iv dsp block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?2 stratix iv simplified dsp operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4 stratix iv operational modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8 stratix iv dsp block resource descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9 input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?10 multiplier and first-stage adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?12 pipeline register stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?13 second-stage adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?13 rounding and saturation stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?14 second adder and output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?14 stratix iv operational mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?15 independent multiplier modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?15 9-, 12-, and 18-bit multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?15 36-bit multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?19 double multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?20 two-multiplier adder sum mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?22 18 x 18 complex multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?24 four-multiplier adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?26 high-precision multiplier adder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?27 multiply accumulate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?29 shift modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?30 rounding and saturation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?32 dsp block control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?34 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?35 contents v september 2012 altera corporation stratix iv device handbook volume 1 chapter 5. clock networks and plls in stratix iv devices clock networks in stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 global clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?3 regional clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?4 periphery clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?6 clock sources per quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?9 clock regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?9 clock network sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 dedicated clock input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 labs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 pll clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?11 clock input connections to the plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?12 clock output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?13 clock control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?14 clock enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?17 clock source control for plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?18 cascading plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?19 plls in stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?19 stratix iv pll hardware overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?23 pll clock i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?24 pll control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?27 pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?27 areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?27 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?27 clock feedback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?28 source synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?29 source-synchronous mode for lvds compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?30 no-compensation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?30 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?31 zero-delay buffer (zdb) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?31 external feedback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?32 clock multiplication and division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?33 post-scale counter cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?34 programmable duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?35 programmable phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?35 programmable bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?37 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?37 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?38 spread-spectrum tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?39 clock switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?39 automatic clock switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?40 manual clock switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?43 guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?43 pll reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?44 pll reconfiguration ha rdware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?45 post-scale counters (c0 to c9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?47 scan chain description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?48 charge pump and loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?50 bypassing a pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?51 dynamic phase-shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?51 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?54 vi contents stratix iv device handbook september 2012 altera corporation volume 1 section ii. i/o interfaces chapter 6. i/o features in stratix iv devices i/o standards support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?2 i/o standards and voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?3 i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?5 modular i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?8 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?17 3.3-v i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?19 external memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?19 high-speed differential i/o with dpa support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?20 programmable current strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?20 programmable slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?21 programmable i/o delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22 programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22 open-drain output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22 bus hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22 programmable pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?23 programmable pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?23 programmable differential output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?23 multivolt i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?23 on-chip termination support and i/o termination schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?24 on-chip series (r s ) termination without calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?25 on-chip series termination with calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?26 left-shift series termination control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?27 on-chip parallel termination with calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ?28 expanded on-chip series termination with calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?29 dynamic on-chip termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?29 lvds input oct (r d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?31 summary of oct assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?31 oct calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?32 oct calibration block location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?32 sharing an oct calibration block on multiple i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?34 oct calibration block modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?35 power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?35 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?36 oct calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?37 serial data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?37 example of using multiple oct calibration blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?38 r s calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?38 termination schemes for i/o standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?38 single-ended i/o standards termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?38 differential i/o standards term ination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?41 lvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?43 differential lvpecl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?44 rsds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?45 mini-lvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?46 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?46 i/o bank restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?46 non-voltage-referenced standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?47 voltage-referenced standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?47 mixing voltage-referenced and non-vo ltage-referenced standards . . . . . . . . . . . . . . . . . . . . . 6?47 contents vii september 2012 altera corporation stratix iv device handbook volume 1 chapter 7. external memory inte rfaces in stratix iv devices memory interfaces pin support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?3 using the r up and r dn pins in a dqs/dq group used for memory interfaces . . . . . . . . . . . . . . 7?26 combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface . . . . . . . . . . . 7?26 rules to combine groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?27 stratix iv external memory interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?29 dqs phase-shift circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?29 dll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?31 phase offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?41 dqs logic block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?43 dqs delay chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?44 update enable circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?44 dqs postamble circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?45 leveling circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?46 dynamic on-chip termination control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?48 i/o element registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?49 delay chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?52 i/o configuration block and dqs configuration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?54 chapter 8. high-speed differential i/o in terfaces and dpa in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?1 locations of the i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?3 lvds channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?4 lvds serdes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?8 altlvds port list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?9 differential transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?11 programmable v od and programmable pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?14 programmable vod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?15 programmable pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?16 differential receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?17 differential i/o termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?18 receiver hardware blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?19 dpa block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?19 synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?20 data realignment block (bit slip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?20 deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?22 receiver data path modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?22 non-dpa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?22 dpa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?24 soft-cdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?25 lvds interface with the use external pll option enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8? 26 left and right plls (pll_lx and pll_rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?29 stratix iv clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?30 source-synchronous timing budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?31 differential data orient ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?31 differential i/o bit posi tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?31 transmitter channel-to-channel skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?33 receiver skew margin for non-dpa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?33 differential pin placemen t guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?38 guidelines for dpa-enabled differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?38 dpa-enabled channels and single-ended i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?38 dpa-enabled channel driving distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?38 using corner and center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ?38 viii contents stratix iv device handbook september 2012 altera corporation volume 1 using both center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?40 guidelines for dpa-disabled diff erential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?42 dpa-disabled channels and single-ended i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?42 dpa-disabled channel driving distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?42 using corner and center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ?42 using both center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?45 section iii. system integration chapter 9. hot socketing and power-on reset in stratix iv devices stratix iv hot-socketing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9?1 stratix iv devices can be driven before power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9?2 i/o pins remain tri-stated during power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9?2 insertion or removal of a stratix iv device from a powere d-up system . . . . . . . . . . . . . . . . . . . . . . 9?2 hot-socketing feature implementation in st ratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9?3 power-on reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9?4 power-on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9?5 chapter 10. configuration, design security, and remote system upgrades in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?1 configuration devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?2 configuration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?2 configuration features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?4 power-on reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?5 vccpgm pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?5 vccpd pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?5 fast passive parallel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?6 fpp configuration using a max ii device as an external host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?6 fpp configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?12 fpp configuration using a microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?16 fast active serial configuration (serial configuration devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10? 16 estimating active serial configuration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?22 programming serial config uration devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?23 guidelines for connecting serial configuration devices on an as interface . . . . . . . . . . . . . . . . . 10?25 passive serial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?25 ps configuration using a max ii device as an external host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?26 ps configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?31 ps configuration using a microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?32 ps configuration using a download cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?32 jtag configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?35 jam stapl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?40 device configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?40 configuration data decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?48 remote system upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?50 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?51 enabling remote update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?53 configuration image types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?54 remote system upgrade mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?54 remote update mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?54 dedicated remote system upgrade circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?57 remote system upgrade registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?58 remote system upgrade control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0?58 remote system upgrade status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?59 contents ix september 2012 altera corporation stratix iv device handbook volume 1 remote system upgrade state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?60 user watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?62 quartus ii software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?63 altremote_update megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?63 design security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?64 stratix iv security protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?65 security against copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?65 security against reverse engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?65 security against tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?65 aes decryption block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?65 flexible security key storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?65 stratix iv design security solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?66 security modes available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?67 volatile key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?67 non-volatile key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?67 non-volatile key with tamper protection bit set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?6 7 no key operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?68 supported configuration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10?68 chapter 11. seu mitigation in stratix iv devices error detection fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?2 configuration error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?2 user mode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?2 automated single-event upset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?5 error detection pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?5 crc_error pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?5 error detection block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?6 error detection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?7 error detection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?8 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?10 recovering from crc errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11?11 chapter 12. jtag boundary-scan testing in stratix iv devices bst architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12?1 bst operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12?2 i/o voltage support in a jtag chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12?4 bst circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12?4 bsdl support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12?4 chapter 13. power management in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?1 stratix iv power technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?2 programmable power technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?2 stratix iv external power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?3 temperature sensing diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?4 external pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?4 additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 x contents stratix iv device handbook september 2012 altera corporation volume 1 september 2012 altera corporation stratix iv device handbook volume 1 chapter revision dates the chapters in this document, stratix iv device handbook, were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1. overview for the stratix iv device family revised: september 2012 part number: siv51001-3.4 chapter 2. logic array blocks and adaptive logic modules in stratix iv devices revised: february 2011 part number: siv51002-3.1 chapter 3. trimatrix embedded memory blocks in stratix iv devices revised: december 2011 part number: siv51003-3.3 chapter 4. dsp blocks in stratix iv devices revised: february 2011 part number: siv51004-3.1 chapter 5. clock networks and plls in stratix iv devices revised: september 2012 part number: siv51005-3.4 chapter 6. i/o features in stratix iv devices revised: september 2012 part number: siv51006-3.4 chapter 7. external memory inte rfaces in stratix iv devices revised: february 2011 part number: siv51007-3.2 chapter 8. high-speed differential i/o in terfaces and dpa in stratix iv devices revised: september 2012 part number: siv51008-3.4 chapter 9. hot socketing and power-on reset in stratix iv devices revised: february 2011 part number: siv51009-3.2 chapter 10. configuration, design security, and re mote system upgrades in stratix iv devices revised: september 2012 part number: siv51010-3.5 chapter 11. seu mitigation in stratix iv devices revised: february 2011 part number: siv51011-3.2 xii chapter revision dates stratix iv device handbook september 2012 altera corporation volume 1 chapter 12. jtag boundary-scan te sting in stratix iv devices revised: february 2011 part number: siv51012-3.2 chapter 13. power management in stratix iv devices revised: february 2011 part number: siv51013-3.2 september 2012 altera corporation stratix iv device handbook volume 1 section i. device core this section provides a complete overview of all features relating to the stratix ? iv device family, which is the most architecturally advanced, high-performance, low-power fpga in the market place. this section includes the following chapters: chapter 1, overview for the stratix iv device family chapter 2, logic array blocks and adaptive logic modules in stratix iv devices chapter 3, trimatrix embedded memory blocks in stratix iv devices chapter 4, dsp blocks in stratix iv devices chapter 5, clock networks and plls in stratix iv devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. i?2 section i: device core stratix iv device handbook september 2012 altera corporation volume 1 siv51001-3.4 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 september 2012 feedback subscribe iso 9001:2008 registered 1. overview for the stratix iv device family altera ? stratix ? iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applicatio ns, allowing you to innovate without compromise. stratix iv fpgas are based on the taiwan semiconductor manufacturing company (tsmc) 40-nm pr ocess technology and surpass all other high-end fpgas, with the highest logic dens ity, most transceivers, and lowest power requirements. the stratix iv device family contains thre e optimized variants to meet different application requirements: stratix iv e (enhanced) fpga s?up to 813,050 logic elements (les), 33,294 kilobits (kb) ram, and 1,288 18 x 18 bit multipliers stratix iv gx transceiver fpgas?up to 531,200 les, 27,376 kb ram, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (cdr)-based transceivers at up to 8.5 gbps stratix iv gt?up to 531,200 les, 27,376 kb ram, 1,288 18 x 18-bit multipliers, and 48 full-duplex cdr-based transceivers at up to 11.3 gbps the complete altera high-end solution includes the lowest risk, lowest total cost path to volume using hardcopy ? iv asics for all the family variants, a comprehensive portfolio of application so lutions customized for end-markets, and the industry leading quartus ? ii software to increase productivity and performance. f for information about upcoming stratix iv device features, refer to the upcoming stratix iv device features document. f for information about changes to the currently published stratix iv device handbook , refer to the addendum to the stratix iv device handbook chapter. this chapter contains the following sections: ?feature summary? on page 1?2 ?architecture features? on page 1?6 ?integrated software platform? on page 1?19 ?ordering information? on page 1?19 september 2012 siv51001-3.4 1?2 chapter 1: overview for the stratix iv device family feature summary stratix iv device handbook september 2012 altera corporation volume 1 feature summary the following list summarizes the stratix iv device family features: up to 48 full-duplex cdr-based transcei vers in stratix iv gx and gt devices supporting data rates up to 8.5 gbps and 11.3 gbps, respectively dedicated circuitry to support physical layer functionality for popular serial protocols, such as pci express (pcie) (pipe) gen1 and gen2, gbps ethernet (gbe), serial rapidio, sonet/sdh, xaui/higig, (oif) cei-6g, sd/hd/3g-sdi, fibre channel, sfi-5, and interlaken complete pcie protocol solution with embedded pcie hard ip blocks that implement phy-mac layer, data link laye r, and transaction layer functionality f for more information, refer to the ip compiler for pci express user guide . programmable transmitter pre-emphasis an d receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium typical physical medium attachment (pma) power consumption of 100 mw at 3.125 gbps and 135 mw at 6.375 gbps per channel 72,600 to 813,050 equivalent les per device 7,370 to 33,294 kb of enhanced trimatri x memory consisting of three ram block sizes to implement true dual-port memory and fifo buffers high-speed digital signal processing (dsp) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full -precision multipliers at up to 600 mhz up to 16 global clocks (gclk), 88 regional clocks (rclk), and 132 periphery clocks (pclk) per device programmable power technology that mini mizes power while maximizing device performance up to 1,120 user i/o pins arranged in 24 modular i/o banks that support a wide range of single-ended and differential i/o standards support for high-speed external memo ry interfaces including ddr, ddr2, ddr3 sdram, rldram ii, qdr ii, and qdr ii+ sram on up to 24 modular i/o banks high-speed lvds i/o support with seri alizer/deserializer (serdes), dynamic phase alignment (dpa), and soft-cdr ci rcuitry at data rates up to 1.6 gbps support for source-synchronous bus standards, including sgmii, gbe, spi-4 phase 2 (pos-phy level 4), sfi-4.1, xsbi, utopia iv, npsi, and csix-l1 pinouts for stratix iv e devices designed to allow migration of designs from stratix iii to stratix iv e with minimal pcb impact chapter 1: overview for the stratix iv device family 1?3 feature summary september 2012 altera corporation stratix iv device handbook volume 1 stratix iv gx devices stratix iv gx devices provide up to 48 full-duplex cdr-based transceiver channels per device: thirty-two out of the 48 transceiver chan nels have dedicated physical coding sublayer (pcs) and physical medium at tachment (pma) circuitry and support data rates between 600 mbps and 8.5 gbps the remaining 16 transceiver channels have dedicated pma-only circuitry and support data rates between 600 mbps and 6.5 gbps 1 the actual number of transceiver channels pe r device varies with device selection. for more information about the exact transc eiver count in each device, refer to table 1?1 on page 1?11 . 1 for more information about transceiver architecture, refer to the transceiver architecture in stratix iv devices chapter. figure 1?1 shows a high-level stratix iv gx chip view. figure 1?1. stratix iv gx chip view (1) note to figure 1?1 : (1) resource counts vary with device selection, package selection, or both. general purpose i/o and memory interface 600 mbps-8.5 gbps cdr-based transceiver general purpose i/o and 150 mbps-1.6 gbps lvds interface with dpa and soft-cdr transceiver block transceiver block transceiver block transceiver block pci express hard ip block pci express hard ip block pci express hard ip block pci express hard ip block general purpose i/o and memory interface pll pll pll pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, embedded memory, clock networks) transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr pll pll pll pll transceiver block transceiver block transceiver block transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr 1?4 chapter 1: overview for the stratix iv device family feature summary stratix iv device handbook september 2012 altera corporation volume 1 stratix iv e device stratix iv e devices provide an excellent solu tion for applications that do not require high-speed cdr-based transceivers, but are logic, user i/o, or memory intensive. figure 1?2 shows a high-level stratix iv e chip view. figure 1?2. stratix iv e chip view (1) note to figure 1?2 : (1) resource counts vary with device selection, package selection, or both. general purpose i/o and memory interface general purpose i/o and 150 mbps-1.6 gbps lvds interface with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and memory interface pll pll pll pll pll pll pll pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, embedded memory, clock networks) general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr chapter 1: overview for the stratix iv device family 1?5 feature summary september 2012 altera corporation stratix iv device handbook volume 1 stratix iv gt devices stratix iv gt devices provide up to 48 cdr-based transceiver channels per device: thirty-two out of the 48 transceiver channels have dedicated pcs and pma circuitry and support data rates between 600 mbps and 11.3 gbps the remaining 16 transceiver channels have dedicated pma-only circuitry and support data rates between 600 mbps and 6.5 gbps 1 the actual number of transceiver channels pe r device varies with device selection. for more information about the exact transc eiver count in each device, refer to table 1?7 on page 1?16 . 1 for more information about stratix iv gt devices and transceiver architecture, refer to the transceiver architecture in stratix iv devices chapter. figure 1?3 shows a high-level stratix iv gt chip view. figure 1?3. stratix iv gt chip view (1) note to figure 1?3 : (1) resource counts vary with device selection, package selection, or both. general p u rpose i/o and memory interface 600 m b ps-11.3 g b ps cdr- b ased transcei v er general p u rpose i/o and u p to 1.6 g b ps l v ds interface w ith dpa and soft-cdr pci express hard ip block pci express hard ip block pci express hard ip block pci express hard ip block transcei v er block transcei v er block transcei v er block transcei v er block general p u rpose i/o and memory interface pll pll pll pll pll pll general p u rpose i/o and memory interface general p u rpose i/o and memory interface pll pll fpga fab r ic (logic elements, dsp, em b edded memory, clock n et w orks) transcei v er block general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr pll pll pll pll general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr transcei v er block transcei v er block transcei v er block transcei v er block 1?6 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 architecture features the stratix iv device family features are di vided into high-speed transceiver features and fpga fabric and i/o features. 1 the high-speed transceiver features apply only to stratix iv gx and stratix iv gt devices. high-speed transceiver features the following sections describe high-speed transceiver features for stratix iv gx and gt devices. highest aggregate data bandwidth up to 48 full-duplex transceiver channels supporting data rates up to 8.5 gbps in stratix iv gx devices and up to 11.3 gbps in stratix iv gt devices. wide range of protocol support physical layer support for the following serial protocols: stratix iv gx?pcie gen1 and gen2, gbe, serial rapidio, sonet/sdh, xaui/higig, (oif) cei-6g, sd/hd/3g-s di, fibre channel, sfi-5, gpon, sas/sata, hypertransport 1.0 and 3.0, and interlaken stratix iv gt?40g/100g ethernet, sfi-s, interlaken, sfi-5.1, serial rapidio, sonet/sdh, xaui/higig, (oif) cei-6g, 3g-sdi, and fibre channel extremely flexible and easy-to-configure transceiver data path to implement proprietary protocols pcie support complete pcie gen1 and gen2 protoc ol stack solution compliant to pci express base specification 2.0 that includes phy-mac, data link, and transaction layer circuitry embedded in pci express hard ip blocks f for more information, refer to the pci express compiler user guide . root complex and end-point applications x1, x4, and x8 lane configurations pipe 2.0-compliant interface embedded circuitry to switch be tween gen1 and gen2 data rates built-in circuitry for electrical idle generation and detection, receiver detect, power state transitions, lane reversal, and polarity inversion 8b/10b encoder and decoder, receiver synchronization state machine, and 300 parts per million (ppm) cl ock compensation circuitry transaction layer support for up to two virtual channels (vcs) chapter 1: overview for the stratix iv device family 1?7 architecture features september 2012 altera corporation stratix iv device handbook volume 1 xaui/higig support compliant to ieee802.3ae specification embedded state machine circuitry to convert xgmii idle code groups (||i||) to and from idle ordered sets (||a||, ||k||, ||r||) at the transmitter and receiver, respectively 8b/10b encoder and decoder, receiver synchronization state machine, lane deskew, and 100 ppm clock compensation circuitry gbe support compliant to ieee802.3-2005 specification automatic idle ordered set (/i1/, /i2/) generation at the transmitter, depending on the current running disparity 8b/10b encoder and decoder, receiver synchronization state machine, and 100 ppm clock compensation circuitry support for other protocol features su ch as msb-to-lsb transmission in sonet/sdh configuration and spread-spect rum clocking in pcie configurations diagnostic features serial loopback from the transmitter serial izer to the receiver cdr for transceiver pcs and pma diagnostics reverse serial loopback pre- and post-cdr to transmitter buffer for physical link diagnostics loopback master and slave capabili ty in pci express hard ip blocks f for more information, refer to the pci express compiler user guide . signal integrity stratix iv devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. these enhancements include: programmable 3-tap transmitter pre-emphas is with up to 8,192 pre-emphasis levels to compensate for pre-cursor and po st-cursor inter-symbol interference (isi) up to 900% boost capability on the first pre-emphasis post-tap user-controlled and adaptive 4-stage rece iver equalization with up to 16 db of high-frequency gain on-die power supply regulators for transmitter and receiver phase-locked loop (pll) charge pump and voltage controlled oscillator (vco) for superior noise immunity on-package and on-chip power supply deco upling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors calibration circuitry for transmitter an d receiver on-chip termination (oct) resistors 1?8 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 fpga fabric an d i/o features the following sections describe the stratix iv fpga fabric and i/o features. device core features up to 531,200 les in stratix iv gx and gt devices and up to 813,050 les in stratix iv e devices, efficien tly packed in unique and innovative adaptive logic modules (alms) ten alms per logic array block (lab) deli ver faster performance, improved logic utilization, and optimized routing programmable power technology, including a variety of process, circuit, and architecture optimizations and innovations programmable power technology available to select power-driven compilation options for reduced static power consumption embedded memory trimatrix embedded memory architecture provides three different memory block sizes to efficiently address the needs of diversified fpga designs: 640-bit mlab 9-kb m9k 144-kb m144k up to 33,294 kb of embedded memory operating at up to 600 mhz each memory block is independently conf igurable to be a single- or dual-port ram, fifo, rom, or shift register digital signal processing (dsp) blocks flexible dsp blocks configurable as 9 x 9- bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 mhz with rounding and saturation capabilities faster operation due to fully pipelined architecture and built-in addition, subtraction, and accumulation units to combine multiplication results optimally designed to support advanced features such as adaptive filtering, barrel shifters, and finite and infinite impulse response (fir and iir) filters clock networks up to 16 global clocks and 88 regional clocks optimally routed to meet the maximum performance of 800 mhz up to 112 and 132 periphery clocks in stratix iv gx and stratix iv e devices, respectively up to 66 (16 gclk + 22 rclk + 28 pclk) clock networks per device quadrant in stratix iv gx and stratix iv gt devices up to 71 (16 gclk + 22 rclk + 33 pclk) clock networks per device quadrant in stratix iv e devices chapter 1: overview for the stratix iv device family 1?9 architecture features september 2012 altera corporation stratix iv device handbook volume 1 plls three to 12 plls per device support ing spread-spectrum input tracking, programmable bandwidth, clock switchov er, dynamic reconfiguration, and delay compensation on-chip pll power supply regulators to minimize noise coupling i/o features sixteen to 24 modular i/o banks per device with 24 to 48 i/os per bank designed and packaged for optimal simultaneous switching noise (ssn) performance and migration capability support for a wide range of industry i/o standards, including single-ended (lvttl/cmos/pci/pcix), differential (lvds/mini-lvds/rsds), voltage-referenced single-ended and di fferential (sstl/hstl class i/ii) i/o standards on-chip series (r s ) and on-chip parallel (r t ) termination with auto-calibration for single-ended i/os and on-chip differential (r d ) termination for differential i/os programmable output drive strength, slew rate control, bus hold, and weak pull-up capability fo r single-ended i/os user i/o:gnd:v cc ratio of 8:1:1 to reduce loop inductance in the package?pcb interface programmable transmitter differential output voltage (v od ) and pre-emphasis for high-speed lvds i/o high-speed differential i/o with dpa and soft-cdr dedicated circuitry on the left and right si des of the device to support differential links at data rates from 150 mbps to 1.6 gbps up to 98 differential serdes in strati x iv gx devices, up to 132 differential serdes in stratix iv e devices, and up to 47 differential serdes in stratix iv gt devices dpa circuitry at the receiver automati cally compensates for channel-to-channel and channel-to-clock skew in source synchronous interfaces soft-cdr circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clocks at up to 1.6 gbps data rate (sgmii and gbe) external memory interfaces support for existing and emerging memo ry interface standards such as ddr sdram, ddr2 sdram, ddr3 sdram, qdrii sram, qdrii+ sram, and rldram ii ddr3 up to 1,067 mbps/533 mhz programmable dq group widths of 4 to 36 bits (includes parity bits) dynamic oct, trace mismatch compensati on, read-write leveling, and half-rate register capabilities provide a robust external memory interface solution 1?10 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 system integration all stratix iv devices support hot socketing four configuration modes: passive serial (ps) fast passive parallel (fpp) fast active serial (fas) jtag configuration ability to perform remote system upgrades 256-bit advanced encryption standard (a es) encryption of configuration bits protects your design against copying, reverse engineering, and tampering built-in soft error detection for configuration ram cells f for more information about how to connect th e pll, external memory interfaces, i/o, high-speed differential i/o, power, and the jtag pins to pcb, refer to the stratix iv gx and stratix iv e device family pin connection guidelines and the stratix iv gt device family pin connection guidelines . chapter 1: overview for the stratix iv device family 1?11 architecture features september 2012 altera corporation stratix iv device handbook volume 1 table 1?1 lists the stratix iv gx device features. table 1?1. stratix iv gx device features (part 1 of 2) feature ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 package option f780 f1152 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 f780 f1152 f1517 f1760 f1932 f780 f1152 f1517 f1760 f1932 f1760 f1932 alms 29,040 42,240 70,300 91,200 116,480 141,440 212,480 les 72,600 105,600 175,750 228,000 291,200 353,600 531,200 0.6 gbps- 8.5 gbps transceivers (pma + pcs) (1) ? 16 ? ? 16 ? ?1624 ? ? 1624 ? ? 16242432 ? ? 162424 32 24 32 0.6 gbps- 6.5 gbps transceivers (pma + pcs) (1) 8 ? 8 16 ? 8 16 ? ? 8 16 ? ? 16 16 ? ? ? ? 16 16 ? ? ? ? ? ? pma-only cmu channels (0.6 gbps- 6.5 gbps) ? 8 ? ? 8 ? ? 8 12 ? ? 8 12 ? ? 8 12 12 16 ? ? 8 12 12 16 12 16 pci express hard ip blocks 121 2 1 2 1 2 2 4 2 4 4 high-speed lvds serdes (up to 1.6 gbps) (4) 28 56 28 28 56 28 44 88 28 44 88 ? 44 88 88 98 ? 44 88 88 98 88 98 spi-4.2 links 1 1 1 2 4 1 2 4 ? 2 4 ? 2 4 4 1?12 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 m9k blocks (256 x 36 bits) 462 660 950 1,235 936 1,248 1,280 m144k blocks (2048 x 72 bits) 16 16 20 22 36 48 64 total memory (mlab+m9k +m144k) kb 7,370 9,564 13,627 17,133 17,248 22,564 27,376 embedded multipliers 18 x 18 (2) 384 512 920 1,288 832 1,040 1,02 4 1,024 plls 3 4 3 4 3 6 8 3 6 8 4 6 8 12 12 4 6 8 12 12 12 12 user i/os (3) 372 488 372 372 48 8 372 56 4 56 4 74 4 372 564 56 4 74 4 289 564 56 4 74 4 88 0 92 0 289 564 56 4 74 4 88 0 920 880 920 speed grade (fastest to slowest) (5) ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2 , ?3 , ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 notes to table 1?1 : (1) the total number of transceivers is divided equally between the left and right side of each device, except for the devices i n the f780 package. these d evices have eight transceiver channels located only on the right side of the device. (2) four multiplier adder mode. (3) the user i/os count from pin-out fil es includes all general purpose i/o, dedicated clock pins, and dual purpose configuratio n pins. transceiver pins and dedicated c onfiguration pins are not included in the pin count. (4) total pairs of high-speed lvds serd es take the lowest channel count of r x /t x . (5) the difference between the st ratix iv gx devices in the ?2 and ?2x speed grades is th e number of available transceiver chann els. the ?2 device allows you to use the transceiver cmu blocks as transceiver channels. the ?2x device does no t allow you to use th e cmu blocks as transceiver channe ls. in addition to the reduc tion of available transcei ver channels in the stra tix iv gx ?2x device, the data rates in the ?2x d evice are limited to 6.5 gbps. table 1?1. stratix iv gx device features (part 2 of 2) feature ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 package option f780 f1152 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 f780 f1152 f1517 f1760 f1932 f780 f1152 f1517 f1760 f1932 f1760 f1932 chapter 1: overview for the stratix iv device family 1?13 architecture features september 2012 altera corporation stratix iv device handbook volume 1 table 1?2 lists the stratix iv gx device package options. 1 on-package decoupling reduces the need for on-board or pcb decoupling capacitors by sati sfying the transient current requirements at higher frequencies. the power delivery network design tool for stratix iv devices accounts for the on-package decoupling and reflects the reduced requ irements for pcb decoupling capacitors. table 1?2. stratix iv gx device package options (1) , (2) device f780 (29 mm x 29 mm) (6) f1152 (35 mm x 35 mm) (6) f1152 (35 mm x 35 mm) (5) , (7) f1517 (40 mm x 40 mm) (5) , (7) f1760 (42.5 mm x 42.5 mm) (7) f1932 (45 mm x 45 mm) (7) ep4sgx70 df29 ? ? hf35 ? ? ? ? ep4sgx110 df29 ? ff35 hf35 ? ? ? ? ep4sgx180 df29 ? ff35 ? hf35 kf40 ? ? ep4sgx230 df29 ? ff35 ? hf35 kf40 ? ? ep4sgx290 ? fh29 (3) ff35 ? hf35 kf40 kf43 nf45 ep4sgx360 ? fh29 (3) ff35 ? hf35 kf40 kf43 nf45 ep4sgx530 ? ? ? ? hh35 (4) kh40 (4) kf43 nf45 notes to table 1?2 : (1) device packages in the same column and marked under the same arro w sign have vertical migration capability. (2) use the pin migration viewer in the pi n planner to verify the pin mi gration compatibility when mi grating devices. for more i nformation, refer to i/o management in the quartus ii handbook, volume 2 . (3) the 780-pin ep4sgx290 and ep4sgx360 devices are availa ble only in 33 mm x 33 mm hy brid flip ch ip package. (4) the 1152-pin and 1517-pin ep4sgx530 devices are available only in 42 .5 mm x 42.5 mm hybrid flip chip packages. (5) when migrating between hybrid and flip chip packages, there is an ad ditional keep-out area. for more information, refer to t he package information dat asheet for altera devices . (6) devices listed in this column are avai lable in ?2x, ?3, and ?4 speed grades. these devices do no t have on-package decoupling capacitors. (7) devices listed in this column are ava ilable in ?2, ?3, and ?4 sp eed grades. these devices have on-package decoupling capacit ors. for more information about on-package decoupli ng capacitor value in each device, refer to table 1?3 . 1?14 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 table 1?3 lists the stratix iv gx device on-package decoupling information. table 1?3. stratix iv gx device on-package decoupling information (1) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct and v ccr (shared) ep4sgx70 hf35 2 ? 1uf + 2 ? 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 ? 470nf + 1 ? 47nf per side ep4sgx110 hf35 2 ? 1uf + 2 ? 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 ? 470nf + 1 ? 47nf per side ep4sgx180 hf35 kf40 2 ? 1uf + 2 ? 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 ? 470nf + 1 ? 47nf per side ep4sgx230 hf35 kf40 2 ? 1 uf + 2 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 ? 470 nf + 1 ? 47 nf per side ep4sgx290 hf35 kf40 kf43 nf45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100nf 1 ? 470 nf + 1 ? 47 nf per side ep4sgx360 hf35 kf40 kf43 nf45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 ? 470 nf + 1 ? 47 nf per side ep4sgx530 hh35 kh40 kf43 nf45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 ? 470 nf + 1 ? 47 nf per side notes to table 1?3 : (1) table 1?3 refers to production devices on-package dec oupling. for more informatio n about decoupling d esign of engineering sample (es) de vices, contact altera technical support . (2) for i/o banks 3(*), 4(*), 7(*), and 8(*) only. ther e is no opd for i/o bank 1(*), 2(*), 5(*), and 6(*). chapter 1: overview for the stratix iv device family 1?15 architecture features september 2012 altera corporation stratix iv device handbook volume 1 table 1?4 lists the stratix iv e device features. table 1?4. stratix iv e device features feature ep4se230 ep4se360 ep4se530 ep4se820 package pin count 780 780 1152 1152 1517 1760 1152 1517 1760 alms 91,200 141,440 212,480 325,220 les 228,000 353,600 531,200 813,050 high-speed lvds serdes (up to 1.6 gbps) (1) 56 56 88 88 112 112 88 112 132 spi-4.2 links 3 3 4 4 6 4 6 6 m9k blocks (256 x 36 bits) 1,235 1,248 1,280 1610 m144k blocks (2048 x 72 bits) 22 48 64 60 total memory (mlab+m9k+ m144k) kb 17,133 22,564 27,376 33,294 embedded multipliers (18 x 18) (2) 1,288 1,040 1,024 960 plls 4 4 8 8 12 12 8 12 12 user i/os (3) 488 488 744 744 976 976 744 (4) 976 (4) 1120 (4) speed grade (fastest to slowest) ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?3, ?4 ?3, ?4 ?3, ?4 notes to table 1?4 : (1) the user i/o count from the pin-out files include all general purpose i/os, dedicated clock pins, and dual purpose configura tion pins. transceiver pins and dedicated configuration pins are not included in the pin count. (2) four multiplier adder mode. (3) total pairs of high-speed lvds serd es take the lowest channel count of r x /t x . (4) this data is preliminary. 1?16 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 table 1?5 summarizes the stratix iv e device package options. table 1?6 lists the stratix iv e on-package decoupling information. table 1?7 lists the stratix iv gt device features. table 1?5. stratix iv e device package options (1) , (2) device f780 (29 mm x 29 mm) (5) , (6) f1152 (35 mm x 35 mm) (5) , (7) f1517 (40 mm x 40 mm) (7) f1760 (42.5 mm x 42.5 mm) (7) ep4se230 f29 ? ? ? ep4se360 h29 (3) f35 ? ? ep4se530 ? h35 (4) h40 (4) f43 ep4se820 ? h35 (4) h40 (4) f43 notes to table 1?5 : (1) device packages in the same column and marked under the same arrow sign have vertical migration capability. (2) use the pin migration viewer in the pin planner to verify the pi n migration compatibility when migrating devices. for more i nformation, refer to i/o management in the quartus ii handbook, volume 2 . (3) the 780-pin ep4se360 device is available only in the 33 mm x 33 mm hybrid flip chip package. (4) the 1152-pin and 1517-pin fo r ep4se530 and ep4se820 devices are available only in the 42.5 mm x 42.5 mm hybrid flip chip package . (5) when migrating between hybrid and flip ch ip packages, there is an ad ditional keep-out area. for mo re information, refer to t he package information datasheet for altera devices . (6) devices listed in this column do not have on-package decoupling capacitors. (7) devices listed in this column have on -package decoupling capacitors. for more information about on-package decoupling capaci tor value for each device, refer to table 1?6 . table 1?6. stratix iv e device on-package decoupling information (1) ordering information v cc v ccio ep4se360 f35 4 ? 1 uf + 4 ? 470 nf 10 nf per bank ep4se530 h35 h40 f43 4 ? 1 uf + 4 ? 470 nf 10 nf per bank ep4se820 h35 h40 f43 4 ? 1 uf + 4 ? 470 nf 10 nf per bank note to table 1?6 : (1) table 1?6 refers to production devices on-package d ecoupling. for more informat ion about deco upling design of engi neering sample (es) devices, contact altera technical support . table 1?7. stratix iv gt device features (part 1 of 2) feature ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g3 ep4s100g4 ep4s100g5 package pin count 1517 1517 1517 1932 1932 1517 1932 alms 91,200 212,480 91,200 116,480 141,440 212,480 les 228,000 531,200 228,000 291,200 353,600 531,200 total transceiver channels 36 36 36 48 48 36 48 chapter 1: overview for the stratix iv device family 1?17 architecture features september 2012 altera corporation stratix iv device handbook volume 1 10g transceiver channels (600 mbps - 11.3 gbps with pma + pcs) 12 12 24 24 24 24 32 8g transceiver channels (600 mbps - 8.5 gbps with pma + pcs) (1) 12 12 0 8 8 0 0 pma-only cmu channels (600 mbps- 6.5 gbps) 12 12 12 16 16 12 16 pcie hard ip blocks 2 2 2 4 4 2 4 high-speed lvds serdes (up to 1.6 gbps) (2) 46 46 46 47 47 46 47 sp1-4.2 links 2 2 2 2 2 2 2 m9k blocks (256 x 36 bits) 1,235 1,280 1,235 936 1,248 1,280 m144k blocks (2048 x 72 bits) 22 64 22 36 48 64 total memory (mlab + m9k + m144k) kb 17,133 27,376 17,133 17,248 22,564 27,376 embedded multipliers 18 x 18 (3) 1,288 1,024 1,288 832 1,024 1,024 plls 8 8 8 12 12 8 12 user i/os (4) , (5) 654 654 654 781 781 654 781 speed grade (fastest to slowest) ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 notes to table 1?7 : (1) you can configure all 10g tr ansceiver channels as 8g transcei ver channels. for example, the ep 4s40g2f40 device has twenty-fo ur 8g transceiver channels and the ep4s100g5f45 devi ce has thirty-two 8g transceiver channels. (2) total pairs of high-speed lvds serd es take the lowest channel count of r x /t x . (3) four multiplier adder mode. (4) the user i/o count from the pin-out files include all genera l purpose i/os, dedicated clock pins, and dual purpose configura tion pins. transceiver pins and dedicated configuration pins are not included in the pin count. (5) this data is preliminary. table 1?7. stratix iv gt device features (part 2 of 2) feature ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g3 ep4s100g4 ep4s100g5 1?18 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 table 1?8 lists the resource counts for the stratix iv gt devices. table 1?9 lists the stratix iv gt on-package decoupling information. table 1?8. stratix iv gt device package options (1) , (2) device 1517 pin (40 mm x 40 mm) (3) 1932 pin (45 mm x 45 mm) stratix iv gt 40 g devices ep4s40g2 f40 ? ep4s40g5 h40 (4) , (5) ? stratix iv gt 100 g devices ep4s100g2 f40 ? ep4s100g3 ? f45 ep4s100g4 ? f45 ep4s100g5 h40 (4) , (5) f45 notes to table 1?8 : (1) this table represents pin compatability; however, it does not includ e hard ip block placement compatability. (2) devices under the same arrow sign have vertical migration capability. (3) when migrating between hybrid and flip chip packages, there is an additional keep-out area. for more information, refer to the altera device package information data sheet . (4) ep4s40g5 and ep4s100g 5 devices with 1517 pi n-count are only available in 42.5- mm x 42.5-mm hybr id flip chip packages. (5) if you are using the hard ip block, migration is not possible. table 1?9. stratix iv gt device on-package decoupling information (1) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct_l/r v ccr_l/r ep4s40g2f40 ep4s100g2f40 2 ? 1 uf + 2 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 100 nf 100 nf ep4s100g3f45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 100 nf 100 nf ep4s100g4f45 ep4s40g5h40 ep4s100g5h40 ep4s100g5f45 notes to table 1?9 : (1) table 1?9 refers to production devices on-package d ecoupling. for more informat ion about deco upling design of engi neering sample (es) devices, contact altera technical support . (2) for i/o banks 3(*), 4(*), 7(*), and 8(*) only. there is no opd for i/o bank 1(*), 2(*), 5(*), and 6(*). chapter 1: overview for the stratix iv device family 1?19 integrated software platform september 2012 altera corporation stratix iv device handbook volume 1 integrated software platform the quartus ii software provides an integrated environment for hdl and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, signaltap ii logic analyzer, and de vice configuration of stratix iv designs. the quartus ii software provides the megawizard ? plug-in manager user interface to generate different functional blocks, such as memory, pll, and digital signal processing logic. for transceivers, the quartus ii software provides the altgx megawizard plug-in manager interface that guides you through configuration of the transceiver based on your application requirements. the stratix iv gx and gt transceivers allow you to implement low-power and reliable high-speed serial interface applications with its fully reconfigurable hardware, optimal signal integrity, and integrated quartus ii software platform. f for more information about the quartus ii software features, refer to the quartus ii handbook . ordering information this section describes the stratix iv e, gt, and gx devices ordering information. figure 1?4 shows the ordering codes for stratix iv gx and e devices. figure 1?4. stratix iv gx and e device packaging ordering information device density transceiver count package type 2, 2x, 3, or 4, w ith 2 b eing the fastest corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins f: fineline bga (fbga) h: hy b rid fineline bga ep4sgx: stratix i v transcei v er d: 8 f: 16 h: 24 k: 36 n : 4 8 ep4se: stratix i v logic/memory 70 110 1 8 0 230 290 360 530 8 20 optional suffix fam i l y s i g n a t u r e operating temperature sp e e d gr ad e ball array dimension 2 ep4sgx 230 c 40 f k es indicates specific de v ice options n :lead-free de v ices es: engineering sample c: commercial temperat u re (t j =0 c to 8 5 c) i: ind u strial temperat u re (t j =?40 c to 100 c) m: military temperat u re (t j =?55 c to 125 c) 1?20 chapter 1: overview for the stratix iv device family ordering information stratix iv device handbook september 2012 altera corporation volume 1 figure 1?5 shows the ordering codes for stratix iv gt devices. document revision history table 1?10 lists the revision history for this chapter. figure 1?5. stratix iv gt device packaging ordering information o device density package type 1, 2, 3 w ith 1 b eing the fastest corresponds to pin co u nt 40 = 1517 pins 45 = 1932 pins f: fineline bga (fbga) h: hy b rid fineline bga 2 = 230k les 3 = 290k les 4 = 360k les 5 = 530k les c: commercial temperature (t j =0 cto85 c) indust rial t emperat ure (t j = 0c to 100c) optional suffix fam i l y s i g n a t u r e operating temperature sp eed gr ade ball array dimension 2 ep4s 230 c 40 f es indicat es specific device opt ions n: lead-free devices i: es: engineering sample aggregate bandwidth ep4s 2 40g 40g 100g table 1?10. document revision history (part 1 of 2) date version changes september 2012 3.4 updated table 1?1 to close fb #30986. updated table 1?2 and table 1?5 to close fb #31127. june 2011 3.3 added military temperature to figure 1?4. february 2011 3.2 updated table 1?7 and table 1?8. applied new template. minor text edits. march 2010 3.1 updated table 1?1, table 1?2, and table 1?7. updated figure 1?3. updated the ?stratix iv gt devices? section. added two new references to the introduction section. minor text edits. chapter 1: overview for the stratix iv device family 1?21 ordering information september 2012 altera corporation stratix iv device handbook volume 1 november 2009 3.0 updated the ?stratix iv device family overview?, ?feature summary?, ?stratix iv gt devices?, ?high-speed transceive r features?, ?fpga fabric and i/o features?, ?highest aggregate data bandwidth?, ?system integr ation?, and ?integrated software platform? sections. added table 1?3, table 1?6, and table 1?9. updated table 1?1, table 1?2, table 1?4, table 1?5, table 1?7, and table 1?8. updated figure 1?3, figure 1?4, and figure 1?5. minor text edits. june 2009 2.4 updated table 1?1. minor text edits. april 2009 2.3 added table 1?5, table 1?6, and figure 1?3. updated figure 1?5. updated table 1?1, table 1?2, table 1?3, and table 1?4. updated ?introduction?, ?feature summary?, ?stratix iv gx devices?, ?stratix iv gt devices?, ?architecture features?, and ?fpga fabric and i/o features? march 2009 2.2 updated ?feature summary?, ?stratix iv gx de vices?, ?stratix iv e device?, ?stratix iv gt devices?, ?signal integrity? removed tables 1-5 and 1-6 updated figure 1?4 march 2009 2.1 updated ?introduction?, ?feature summary?, ?s tratix iv device diagnostic features?, ?signal integrity?, ?clock networks?,?high-sp eed differential i/o with dpa and soft- cdr?, ?system integration?, and ?ordering information? sections. added ?stratix iv gt 100g devices? and ?stratix iv gt 100g transceiver bandwidth? sections. updated table 1?1, table 1?2, table 1?3, and table 1?4. added table 1?5 and table 1?6. updated figure 1?3 and figure 1?4. added figure 1?5. removed ?referenced documents? section. november 2008 2.0 updated ?feature summary? on page 1?1. updated ?stratix iv device diagnostic features? on page 1?7. updated ?fpga fabric and i/o features? on page 1?8. updated table 1?1. updated table 1?2. updated ?table 1?5 shows the total number of transceivers available in the stratix iv gt device.? on page 1?15. july 2008 1.1 revised ?introduction?. may 2008 1.0 initial release. table 1?10. document revision history (part 2 of 2) date version changes 1?22 chapter 1: overview for the stratix iv device family ordering information stratix iv device handbook september 2012 altera corporation volume 1 siv51002-3.1 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 2. logic array blocks and adaptive logic modules in stratix iv devices this chapter describes the features of the logic array blocks (labs) in the stratix ? iv core fabric. labs are made up of adaptive logic modules (alms) that you can configure to implement logic functions, arithmetic functions, and register functions. labs and alms are the basic building bloc ks of the stratix iv device. use these to configure logic, arithmetic, and register functions. the alm provides advanced features with efficient logic usage an d is completely backward-compatible. this chapter contains the following sections: ?logic array blocks? ?adaptive logic modules? on page 2?5 logic array blocks each lab consists of ten alms, various ca rry chains, shared ar ithmetic chains, lab control signals, local interconnect, and re gister chain connection lines. the local interconnect transfers signals between alms in the same lab. the direct link interconnect allows the lab to drive into th e local interconnect of its left and right neighbors. register chain connections transf er the output of the alm register to the adjacent alm register in the lab. the quartus ? ii compiler places associated logic in the lab or adjacent labs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. february 2011 siv51002-3.1 2?2 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices logic array blocks stratix iv device handbook february 2011 altera corporation volume 1 figure 2?1 shows the stratix iv lab structure and interconnects. the lab of the stratix iv device has a derivative called memory lab (mlab), which adds look-up table (lut)-based sram capability to the lab, as shown in figure 2?2 . the mlab supports a maximum of 640 bits of simple dual-port static random access memory (sram). you can configure each alm in an mlab as either a 64 1 or a 32 2 block, resulting in a configuratio n of either a 64 10 or a 32 20 simple dual-port sram block. mlab and lab blocks always coexist as pairs in all stratix iv families. mlab is a superset of the lab and includes all lab features. figure 2?1. stratix iv lab structure and interconnects direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block alms mlab c4 c12 r20 r4 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?3 logic array blocks february 2011 altera corporation stratix iv device handbook volume 1 f for more information about the mlab, refer to the chapter. figure 2?2. stratix iv lab and mlab structure note to figure 2?2 : (1) you can use the mlab alm as a re gular lab alm or configure it as a dual-port sram, as shown. mlab lab lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) alm alm alm alm alm alm alm alm alm alm lab control block lab control block 2?4 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices logic array blocks stratix iv device handbook february 2011 altera corporation volume 1 lab interconnects the lab local interconnect can drive alms in the same lab. it is driven by column and row interconnects and alm output s in the same lab. neighboring labs/mlabs, m9k ram blocks, m144k blocks , or digital signal processing (dsp) blocks from the left or right can also drive the lab?s local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. each lab can drive 30 alms through fast-local and direct-link interconnects. figure 2?3 shows the direct-link connection. lab control signals each lab contains dedicated logic for driving control signals to its alms. control signals include three clocks, three cloc k enables, two asynchronous clears, a synchronous clear, and synchronous load cont rol signals. this gives a maximum of 10 control signals at a time. although you generally use synchronous-load and clear signals when implementing counters, you can also use them with other functions. each lab has two unique clock sources and three clock enable signals, as shown in figure 2?4 . the lab control block can generate up to three clocks using two clock sources and three clock enable signals. each lab?s clock and clock enable signals are linked. for example, any alm in a particular lab using the labclk1 signal also uses the labclkena1 signal. if the lab uses both the rising and falling edges of a clock, it also uses two lab-wide clock signals. de-asserting the clock enable signal turns off the corresponding lab-wide clock. figure 2?3. direct-link connection alm s direct-link interconnect to right direct-link interconnect from the right lab, trimatrix memory b lock, dsp b lock, or ioe o u tp u t direct-link interconnect from the left lab, trimatrix memory b lock, dsp b lock, or ioe o u tp u t local i n te r co nn ect lab alm s direct-link interconnect to left mlab chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?5 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 the lab row clocks [5..0] and lab local interconnects generate the lab-wide control signals. the multitrack interconnect?s inherent low skew allows clock and control signal distribution in addition to data. adaptive logic modules the alm is the basic building block of logic in the stratix iv architecture. it provides advanced features with efficient logic usage. each alm contains a variety of lut-based resources that can be divided between two combinational adaptive luts (aluts) and two registers. with up to eigh t inputs for the two combinational aluts, one alm can implement various combinations of two functions. this adaptability allows an alm to be completely back ward-compatible with four-input lut architectures. one alm can also implement any function with up to six inputs and certain seven-input functions. figure 2?4. lab-wide control signals dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclk2 syncload labclkena0 or asyncload or labpreset labclk0 labclk1 labclr1 labclkena1 labclkena2 labclr0 synclr 6 6 6 there are two unique clock signals per lab. 2?6 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 in addition to the adaptive lut-base d resources, each alm contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. through these de dicated resources, an alm can efficiently implement various arithmetic functions and shift registers. each alm drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link. figure 2?5 shows a high-level block diagram of the stratix iv alm. figure 2?5. high-level block diagram of the stratix iv alm dq to general or local ro u ting reg0 to general or local ro u ting datae0 dataf0 reg_chain_in reg_chain_o u t adder0 dataa data b datac datad datae1 dataf1 dq to general or local ro u ting reg1 to general or local ro u ting adder1 carry_in carry_o u t com b inational/memory alut0 6-inp u t lut 6-inp u t lut shared_arith_o u t shared_arith_in com b inational/memory alut1 la b clk chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?7 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 figure 2?6 shows a detailed view of all the connections in an alm. one alm contains two programmable registers . each register has data, clock, clock enable, synchronous and asynchronous clear, and synchronous load and clear inputs. global signals, general-purpose i/o pins, or any internal logic can drive the register?s clock and clear-control signals. either general-purpose i/o pins or internal logic can drive the clock enable. for combinational fu nctions, the register is bypassed and the output of the lut drives direct ly to the outputs of an alm. each alm has two sets of outputs that drive the local, row, and column routing resources. the lut, adder, or register outp uts can drive these output drivers (refer to figure 2?6 ). for each set of output drivers, two alm outputs can drive column, row, or direct-link routing connections. one of these alm outputs can also drive local interconnect resources. this allows the lut or adder to drive one output while the register drives another output. figure 2?6. stratix iv alm connection details d q + reg_chain_in aclr[1:0] sclr syncload clk[2:0] carry_in dataf0 datae0 dataa datab datac1 datae1 dataf1 shared_arith_out carry_out reg_chain_out clr d q clr shared_arith_in local interconnect row, column direct link routing row, column direct link routing local interconnect 4-input lut 4-input lut 3-input lut 3-input lut 3-input lut 3-input lut + datac0 v cc gnd row, column direct link routing row, column direct link routing 2?8 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 this feature, called register packing, impr oves device utilization because the device can use the register and the combinationa l logic for unrelated functions. another special packing mode allows the register output to feed back into the lut of the same alm so that the register is packed with it s own fan-out lut. this provides another mechanism for improved fitting. the alm can also drive out registered and unregistered versions of the lut or adder output. alm operating modes the stratix iv alm operates in one of the following modes: normal extended lut arithmetic shared arithmetic lut-register each mode uses alm resources differently. in each mode, eleven available inputs to an alm?the eight data inputs from the lab local interconnect, carry-in from the previous alm or lab, the shared arithmetic chain connection from the previous alm or lab, and the register chain connectio n?are directed to different destinations to implement the desired logic function. lab-wide signals provide clock, asynchronous clear, synchronous clear, sync hronous load, and clock enable control for the register. these lab-wide signal s are available in all alm modes. for more information about the lab- wide control signals, refer to ?lab control signals? on page 2?4 . the quartus ii software and supported third-party synthesis tools, in conjunction with parameterized functions such as th e library of parameterized modules (lpm) functions, automatically choose the approp riate mode for common functions such as counters, adders, subtractors, and arithmetic functions. chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?9 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 normal mode normal mode is suitable for general logic applications and combinational functions. in this mode, up to eight data inputs from the lab local interconnect are inputs to the combinational logic. normal mode allows two functions to be implemented in one stratix iv alm, or a single function of up to six inputs. the al m can support certain combinations of completely independent functions and various combinations of functions that have common inputs. figure 2?7 shows the supported lut combinations in normal mode. normal mode provides complete backwa rd-compatibility with four-input lut architectures. figure 2?7. alm in normal mode (1) note to figure 2?7 : (1) combinations of functions with fewer in puts than those shown are also supported. for example, combinatio ns of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, and 5 and 2. 6-inp u t lut dataf0 datae0 dataf0 datae0 dataa data b dataa data b data b datac datac dataf0 datae0 dataa datac 6-inp u t lut datad datad datae1 com b o u t0 com b o u t1 com b o u t0 com b o u t1 com b o u t0 com b o u t1 dataf1 datae1 dataf1 datad datae1 dataf1 4-inp u t lut 4-inp u t lut 4-inp u t lut 6-inp u t lut dataf0 datae0 dataa data b datac datad com b o u t0 5-inp u t lut 5-inp u t lut dataf0 datae0 dataa data b datac datad com b o u t0 com b o u t1 datae1 dataf1 5-inp u t lut dataf0 datae0 dataa data b datac datad com b o u t0 com b o u t1 datae1 dataf1 5-inp u t lut 3-inp u t lut 2?10 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 for the packing of 2 five-input functions in to one alm, the functions must have at least two common inputs. the common inputs are dataa and datab . the combination of a four-input function with a five-input function requires one common input (either dataa or datab ). in the case of implementing 2 six-input fu nctions in one alm, four inputs must be shared and the combinational function must be the same. in a sparsely used device, functions that could be placed in one alm may be implemented in separate alms by the quartus ii software to achieve the best possible performance. as a device begins to fill up, the quartus ii software automatically uses the full potential of the stratix iv alm. the quartus ii compiler automatica lly searches for functions using common inputs or completely independ ent functions to be placed in one alm to make efficient use of device resources. in addition, yo u can manually control resource usage by setting location assignments. you can implement any six-input function using inputs dataa , datab , datac , datad , and either datae0 and dataf0 or datae1 and dataf1 . if you use datae0 and dataf0 , the output is driven to register0 , and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (refer to figure 2?8 ). if you use datae1 and dataf1 , the output either drives to register1 or bypasses register1 and drives to the interconnect using the bott om set of output drivers. the quartus ii compiler automatically selects the inputs to the lut. alms in normal mode support register packing. figure 2?8. input function in normal mode (1) notes to figure 2?8 : (1) if you use datae1 and dataf1 as inputs to a si x-input function, datae0 and dataf0 are available for register packing. (2) the dataf1 input is available for register packing only if the six-input function is unregistered. 6-inp u t lut dataf0 datae0 dataa data b datac datad datae1 dataf1 dq dq to general or local ro u ting to general or local ro u ting to general or local ro u ting reg0 reg1 the s e i n p u t s a r e available fo r r egi s te r packi n g. (2) la b clk chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?11 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 extended lut mode use extended lut mode to implement a specific set of seven-input functions. the set must be a 2-to-1 multiplexer fed by two ar bitrary five-input functions sharing four inputs. figure 2?9 shows the template of supported seven-input functions using extended lut mode. in this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. functions that fit into the template shown in figure 2?9 occur naturally in designs. these functions often appear in designs as ?if-else? statements in verilog hdl or vhdl code. figure 2?9. template for supported seven-input functions in extended lut mode note to figure 2?9 : (1) if the seven-input function is unregistered , the unused eighth input is available fo r register packing. the second register, reg1 , is not available. datae0 com b o u t0 5-inp u t lut 5-inp u t lut datac dataa data b datad dataf0 datae1 dataf1 dq to general or local ro u ting to general or local ro u ting reg0 thi s i n p u t i s available fo r r egi s te r packi n g. (1) 2?12 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 arithmetic mode arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. the al m in arithmetic mode uses two sets of 2 four-input luts along with two dedicated full adders. the dedicated adders allow the luts to be available to perform pre-adder logic; therefore, each adder can add the output of 2 four-input functions. the four luts share dataa and datab inputs. as shown in figure 2?10 , the carry-in signal feeds to adder0 and the carry-out from adder0 feeds to the carry-in of adder1 . the carry-out from adder1 drives to adder0 of the next alm in the lab. alms in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. while operating in arithmetic mode, the alm can support simultaneous use of the adder?s carry output along with combinational logic outputs. in this operation, adder output is ignored. using the adder with combinational logic output provides resource savings of up to 50% for functi ons that can use this ability. arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchron ous clear, and synchronous load. the lab local interconnect data inputs generate th e clock enable, counter enable, synchronous up/down, and add/subtract control sign als. these control signals are good candidates for the inputs that are shared between the four luts in the alm. the synchronous clear and synchronous load opti ons are lab-wide signals that affect all registers in the lab. these signals can also be individually disabled or enabled per register. the quartus ii software automatically places any registers that are not used by the counter into other labs. figure 2?10. alm in arithmetic mode datae0 carry_in carry_o u t dataa data b datac datad datae1 dq dq to general or local ro u ting to general or local ro u ting reg0 reg1 to general or local ro u ting to general or local ro u ting 4-inp u t lut 4-inp u t lut 4-inp u t lut 4-inp u t lut adder1 adder0 dataf0 dataf1 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?13 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 carry chain the carry chain provides a fast carry function between the dedicated adders in arithmetic or shared-arithmetic mode. the two-bit carry select feature in stratix iv devices halves the propagation delay of ca rry chains within the alm. carry chains can begin in either the first alm or the fifth alm in the lab. the final carry-out signal is routed to the alm, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically cr eates carry-chain logic during design processing, or you can create it manual ly during design entry. parameterized functions such as lpm functions automaticall y take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carry chains lo nger than 20 (10 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to trimatrix memory and dsp blocks. a carry chai n can continue as far as a full column. to avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the la b can support carry chains that only use either the top half or bottom half of the la b before connecting to the next lab. this leaves the other half of the alms in th e lab available for implementing narrower fan-in functions in normal mode. carry chains that use the top five alms in the first lab carry into the top half of the alms in the next lab within the column. carry chains that use the bottom fi ve alms in the first lab carry into the bottom half of the alms in the next lab within the column. in every alternate lab column, the top half can be bypassed; in the other mlab colu mns, the bottom half can be bypassed. for more information about carry-chain interconnects, refer to ?alm interconnects? on page 2?18 . 2?14 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 shared arithmetic mode in shared arithmetic mode, the alm can implement a three-input add within the alm. in this mode, the alm is configured with 4 four-input luts. each lut either computes the sum of three inputs or the carry of three inputs. the output of the carry computation is fed to the next adder (either to adder1 in the same alm or to adder0 of the next alm in the lab) using a dedicate d connection called the shared arithmetic chain. this shared arithmetic chain can si gnificantly improve the performance of an adder tree by reducing the number of summa tion stages required to implement an adder tree. figure 2?11 shows the alm using this feature. you can find adder trees in many differen t applications. for example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or de-spread data that was transmitted using spread-spectrum technology. shared arithmetic chain the shared arithmetic chain available in enhanced arithmetic mode allows the alm to implement a three-input add. this signif icantly reduces the resources necessary to implement large adder trees or correlator functions. shared arithmetic chains can begin in eith er the first or sixth alm in the lab. the quartus ii compiler creates shared arithmetic chains longer than 20 (10 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long shared arithmet ic chain runs vertically, allowing fast horizontal connections to the trimatrix me mory and dsp blocks. a shared arithmetic chain can continue as far as a full column. figure 2?11. alm in shared arithmetic mode datae0 carry_in shared_arith_in shared_arith_o u t carry_o u t dataa data b datac datad datae1 dq dq to general or local ro u ting to general or local ro u ting reg0 reg1 to general or local ro u ting to general or local ro u ting 4-inp u t lut 4-inp u t lut 4-inp u t lut 4-inp u t lut la b clk chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?15 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 similar to the carry chains, the top and bottom halves of shared arithmetic chains in alternate lab columns can be bypassed. this capability allows the shared arithmetic chain to cascade through half of the alms in an lab while leaving the other half available for narrower fan-in functionalit y. every other lab column is top-half by-passable, while the other lab co lumns are bottom-half by-passable. for more information about the shared ar ithmetic chain interconnect, refer to ?alm interconnects? on page 2?18 . lut-register mode lut-register mode allows third-register capability within an alm. two internal feedback loops allow combinational alut1 to implement the master latch and combinational alut0 to implement the slave latch needed for the third register. the lut register shares its clock, clock enable , and asynchronous clear sources with the top dedicated register. figure 2?12 shows the register constructed using two combinational blocks within the alm. figure 2?12. lut register from two combinational blocks 4-input lut 5-input lut clk aclr datain(datac) sclr sumout combout lut regout sumout combout 2?16 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 figure 2?13 shows the alm in lut-register mode. figure 2?13. alm in lut-register mode with three-register capability datain aclr sclr regout latchout datain sdata regout aclr datain sdata regout aclr dc1 e0 f1 e1 f0 clk [2:0] aclr [1:0] reg_chain_in lelocal 0 leout 0 a leout 0 b reg_chain_out lelocal 1 leout 1 a leout 1 b chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?17 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 register chain in addition to general routing outputs, alms in the lab have register-chain outputs. register-chain routing allows registers in the same lab to be cascaded together. the register-chain interconnect allows the lab to use luts for a single combinational function and the registers to be used for an unrelated shift-register implementation. these resources speed up connections betwee n alms while saving local interconnect resources (refer to figure 2?14 ). the quartus ii compiler automatically takes advantage of these resources to im prove utilization and performance. for more information about the regi ster chain interconnect, refer to ?alm interconnects? on page 2?18 . figure 2?14. register chain within the lab (1) note to figure 2?14 : (1) you can use the combinational or adder logic to implement an unrelated, un-registered function. dq to general or local routing reg0 to general or local routing reg_chain_in adder0 dq to general or local routing reg1 to general or local routing adder1 dq to general or local routing reg0 to general or local routing reg_chain_out adder0 dq to general or local routing reg1 to general or local routing adder1 from previous alm within the lab to next alm within the lab combinational logic combinational logic labclk 2?18 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 alm interconnects there are three dedicated paths between the alms?register cascade, carry chain, and shared arithmetic chain. stratix iv de vices include an enhanced interconnect structure in labs for routing shared arithm etic chains and carry chains for efficient arithmetic functions. the register chain conne ction allows the register output of one alm to connect directly to the register inpu t of the next alm in the lab for fast shift registers. these alm-to-alm connections bypass the local interconnect. the quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?15 shows the shared arithmetic chain, carry chain, and register chain interconnects. clear and preset logic control lab-wide signals control the logic for the register?s clear signal. the alm directly supports an asynchronous clear function. yo u can achieve the register preset through the quartus ii software?s not-gate push-back logic option. each lab supports up to two clears. stratix iv devices provide a device-wide reset pin ( dev_clrn ) that resets all the registers in the device. an option set befo re compilation in the quartus ii software controls this pin. this device-wide reset overrides all other control signals. figure 2?15. shared arithmetic chain, carry chain, and register chain interconnects alm 1 alm 2 alm 3 alm 4 alm 5 alm 6 carry chain & shared arithmetic chain routing to adjacent alm local interconnect register chain routing to adjacent alm's register input local interconnect routing among alms in the lab alm 7 alm 8 alm 9 alm 10 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?19 adaptive logi c modules february 2011 altera corporation stratix iv device handbook volume 1 lab power managem ent techniques the following techniques are used to mana ge static and dynamic power consumption within the lab: to save ac power, the quartus ii software forces all adder inputs low when alm adders are not in use. stratix iv labs operate in high-performance mode or low-power mode. the quartus ii software automatically chooses the appropriate mode for the lab, based on the design, to optimize speed versus leakage trade-offs. clocks represent a significant portion of dynamic power consumption due to their high switching activity and long paths. the lab clock that distributes a clock signal to registers within an lab is a significant contributor to overall clock power consumption. each lab?s clock and clock enable signal are linked. for example, a combinational alut or register in a particular lab using the labclk1 signal also uses the labclkena1 signal. to disable lab-wide clock power consumption without disabling the entire clock tree, use lab-wide clock enable to gate the lab-wide clock. the quartus ii software automatically promotes register-level clock enable signals to the lab-level. al l registers within the lab that share a common clock and clock enable are controll ed by a shared, gated clock. to take advantage of these clock enables, use a cl ock-enable construct in your hdl code for the registered logic. f for more information about implementing static and dynamic power consumption within the lab, refer to the power optimization chapter in volume 2 of the quartus ii handbook . document revision history table 2?1 lists the revision history for this chapter. table 2?1. document revision history date version changes february 2011 3.1 updated figure 2?6 . applied new template. minor text edits. november 2009 3.0 updated graphics. minor text edits. june 2009 2.2 removed the conclusion section. added introductory sentences to improve search ability. minor text edits. march 2009 2.1 removed ?referenced documents? section. november 2008 2.0 updated figure 2?6. made minor editorial changes. may 2008 1.0 initial release. 2?20 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook february 2011 altera corporation volume 1 siv51003-3.3 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 december 2011 feedback subscribe iso 9001:2008 registered 3. trimatrix embedded memory blocks in stratix iv devices this chapter describes the trimatrix embedded memory blocks in stratix ? iv devices. trimatrix embedded memory blocks provide three different sizes of embedded sram to efficiently address the needs of stratix iv fpga designs. trimatrix memory includes 640-bit memory logic array blocks (mlabs), 9-kbit m9k blocks, and 144-kbit m144k blocks. mlabs have been opti mized to implement filter delay lines, small fifo buffers, and shift registers. you can use the m9k blocks for general purpose memory applications and the m144 k blocks for processor code storage, packet buffering, and video frame buffering. you can independently configure each embedded memory block to be a single- or dual-port ram, fifo buffer, rom, or shift register using the quartus ? ii megawizard? plug-in manager. you can stitch together multiple blocks of the same type to produce larger memories with mi nimal timing penalty. trimatrix memory provides up to 31,491 kbits of embedded sram at up to 600 mhz operation. this chapter contains the following sections: ?overview? ?memory modes? on page 3?9 ?clocking modes? on page 3?17 ?design considerations? on page 3?18 overview table 3?1 lists the features supported by the three sizes of trimatrix memory. table 3?1. summary of trimatrix memory features (part 1 of 2) feature mlabs m9k blocks m144k blocks maximum performance 600 mhz 600 mhz 540 mhz total ram bits (including parity bits) 640 9216 147,456 december 2011 siv51003-3.3 3?2 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook december 2011 altera corporation volume 1 configurations (depth width) 648 649 64 10 32 16 32 18 32 20 8k 1 4k 2 2k 4 1k 8 1k 9 512 16 512 18 256 32 256 36 16k 8 16k 9 8k 16 8k 18 4k 32 4k 36 2k 64 2k 72 parity bits supported supported supported byte enable supported supported supported packed mode ? supported supported address clock enable supported supported supported single-port memory supported supported supported simple dual-port memory supported supported supported true dual-port memory ? supported supported embedded shift register supported supported supported rom supported supported supported fifo buffer supported supported supported simple dual-port mixed width support ? supported supported true dual-port mixed width support ? supported supported memory initialization file ( .mif ) supported supported supported mixed clock mode supported supported supported power-up condition outputs cleared if registered, otherwise reads memory contents outputs cleared outputs cleared register clears output registers output registers output registers write/read operation triggering write: falling clock edges read: rising clock edges write and read: rising clock edges write and read: rising clock edges same-port read-during-write outputs set to don?t care outputs set to old data or new data outputs set to old data or new data mixed-port read-during-write outputs set to old data, new data, or don?t care (1) outputs set to old data or don?t care outputs set to old data or don?t care ecc support soft ip support using the quartus ii software soft ip support using the quartus ii software built-in support in 64-wide sdp mode or soft ip support using the quartus ii software note to table 3?1 : (1) the mixed-port read-during-write options of new data or old data are only supported for mlabs when y ou use both the read address registers and the output registers. table 3?1. summary of trimatrix memory features (part 2 of 2) feature mlabs m9k blocks m144k blocks chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?3 overview december 2011 altera corporation stratix iv device handbook volume 1 table 3?2 lists the capacity and distribution of the trimatrix memory blocks in each stratix iv family member. trimatrix memory block types while the m9k and m144k memory blocks are dedicated resources, the mlabs are dual-purpose blocks. they can be configured as regular logic array blocks (labs) or as mlabs. ten adaptive logic modules (alms) make up one mlab. you can configure each alm in an mlab as either a 64 1 or a 32 2 block, resulting in a 64 10 or 32 20 simple dual-port sram block in a single mlab. parity bit support all trimatrix memory blocks have built-in pa rity-bit support. the ninth bit associated with each byte can store a parity bit or se rve as an additional data bit. no parity function is actually perf ormed on the ninth bit. byte enable support all trimatrix memory blocks support byte en ables that mask the input data so that only specific bytes of data are written. the unwritten bytes retain the previously written values. the write enable ( wren ) signals, along with the byte enable ( byteena ) signals, control the ram blocks? write operations. table 3?2. trimatrix memory capacity and distribution in stratix iv devices device mlabs m9k blocks m144k blocks total dedicated ram bits (dedicated memory blocks only) (kb) total ram bits (including mlabs) (kb) ep4se230 4,560 1,235 22 14,283 17,133 ep4se360 7,072 1,248 48 18,144 22,564 ep4se530 10,624 1,280 64 20,736 27,376 ep4se820 16,261 1,610 60 23,130 33,294 ep4sgx70 1,452 462 16 6,462 7,370 ep4sgx110 2,112 660 16 8,244 9,564 ep4sgx180 3,515 950 20 11,430 13,627 ep4sgx230 4,560 1,235 22 14,283 17,133 ep4sgx290 5,824 936 36 13,608 17,248 ep4sgx360 7,072 1,248 48 18,144 22,564 ep4sgx530 10,624 1,280 64 20,736 27,376 ep4s40g2 4,560 1,235 22 14,283 17,133 ep4s40g5 10,624 1280 64 20,736 27,376 ep4s100g2 4,560 1,235 22 14,283 17,133 ep4s100g3 5,824 936 36 13,608 17,248 ep4s100g4 7,072 1,248 48 18,144 22,564 ep4s100g5 10,624 1,280 64 20,736 27,376 3?4 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook december 2011 altera corporation volume 1 the default value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. the byte enable registers have no clear port. when using parity bits on the m9k and m144k blocks, the byte enable controls all nine bits (eight bits of data plus one parity bit). when usin g parity bits on the mlab, the byte-enable controls al l 10 bits in the widest mode. the msb for the byteena signal corresponds to the msb of the data bus and the lsb of the byteena signal corresponds to the lsb of the data bus. for example, if you use a ram block in 18 mode, with byteena = 01 , data[8..0] is enabled, and data[17..9] id disabled. similarly, if byteena = 11 , both data[8..0] and data[17..9] are enabled. byte enables are active high. 1 you cannot use the byte enable feature when using the error correction coding (ecc) feature on m144k blocks. 1 byte enables are only supported for true dual-port memory configurations when both the porta and portb data widtbyths of the individual m9k memory blocks are multiples of 8 or 9 bits. for example, if you implement a mixed data width memory configured with porta = 32 and portb = 8 as two separate 16 x 4 bit memories, you cannot use the byte enable feature. figure 3?1 shows how the write enable ( wren ) and byte enable ( byteena ) signals control the operations of the ram blocks. when a byte-enable bit is de -asserted during a write cycle, the corresponding data byte output can appear as either a ?don?t care? value or the current data at that location. the output value for the masked byte is controllable using the quartus ii software. when a byte-enable bit is asserted during a write cycle, the corresponding data byte output also depends on the se tting chosen in the quartus ii software. figure 3?1. byte enable functional waveform inclock wren address data don't care: q (asynch) byteena xxxx abcd xxxx xx 10 01 11 xx an a0 a1 a2 a0 a1 a2 abcd ffff ffff abff ffff ffcd contents at a0 contents at a1 contents at a2 doutn abxx xxcd abcd abff ffcd abcd doutn abff ffcd abcd abff ffcd abcd current data: q (asynch) chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?5 overview december 2011 altera corporation stratix iv device handbook volume 1 packed mode support stratix iv m9k and m144k blocks support packed mode. the packed mode feature packs two independent single-port rams into one memory block. the quartus ii software automatically implements packed mode where appropriate by placing the physical ram block into true dual-port mode and using the msb of the address to distinguish between the two logical rams. th e size of each independent single-port ram must not exceed half of the target block size. 3?6 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook december 2011 altera corporation volume 1 address clock enable support all stratix iv memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled ( addressstall = 1 ). when the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. the default value for the address clock enable signals is low (disabled). figure 3?2 shows an address clock enable block diagram. the address clock enable is referred to by the port name addressstall . figure 3?3 shows the address clock enable waveform during the read cycle. figure 3?2. address clock enable figure 3?3. address clock enable during read cycle waveform address[0] address[n] addressstall clock 1 0 address[0] register address[n] register address[n] address[0] 1 0 inclock rden rdaddress q (synch) a0 a1 a2 a3 a4 a5 a6 q (asynch) an a0 a4 a5 latched address (inside memory) dout0 dout1 dout4 dout4 dout5 addressstall a1 doutn-1 doutn doutn dout0 dout1 chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?7 overview december 2011 altera corporation stratix iv device handbook volume 1 figure 3?4 shows the address clock enable waveform during the write cycle. mixed width support m9k and m144k memory blocks support mi xed data widths inherently. mlabs can support mixed data widths through emulat ion using the quartus ii software. when using simple dual-port, true dual-port, or fifo modes, mixed width support allows you to read and write different data widths to a memory block. for more information about the different widths supported per memory mode, refer to ?memory modes? on page 3?9 . 1 mlabs do not support mixed-width fifo mode. asynchronous clear stratix iv trimatrix memory blocks support asynchronous clears on output latches and output registers. therefore, if your ram is not using output registers, you can still clear the ram outputs using the output latch asynchronous clear. figure 3?5 shows a waveform of the output la tch asynchronous clear function. you can selectively enable asynchronous clears per logical memory using the quartus ii ram megawizard plug-in manager. f for more information, refer to the internal memory (ram and rom) user guide . figure 3?4. address clock enable during the write cycle waveform inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0 a4 a5 latched address (inside memory) addressstall a1 data 00 01 02 03 04 05 06 contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 xx 04 xx 00 03 01 xx 02 xx xx xx 05 figure 3?5. output latch asynchronous clear waveform aclr aclr at latch q outclk 3?8 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook december 2011 altera corporation volume 1 error correction code (ecc) support stratix iv m144k blocks have built-in support for error correction code (ecc) when in 64-wide simple dual-port mode. ecc allows you to detect and correct data errors in the memory array. the m144k blocks have a single-error-correction double-error-detection (secded) implem entation. secded can detect and fix a single bit error in a 64-bit word, or detect two bit errors in a 64-bit word. it cannot detect three or more errors. the m144k ecc status is communicate d using a three-bit status flag eccstatus[2..0] . the status flag can be either registered or unregistered. when registered, it uses the same clock and as ynchronous clear signals as the output registers. when unregistered, it cannot be asynchronously cleared. table 3?3 lists the truth table for the ecc status flags. 1 you cannot use the byte enable feature when ecc is engaged. 1 read-during-write ?old data mode? is not supported when ecc is engaged. table 3?3. truth table for ecc status flags status eccstatus[2] eccstatus[1] eccstatus[0] no error 000 single error and fixed 0 1 1 double error and no fix 1 0 1 illegal 0 0 1 illegal 0 1 0 illegal 1 0 0 illegal 1 1 x chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?9 memory modes december 2011 altera corporation stratix iv device handbook volume 1 figure 3?6 shows a diagram of the ecc block of the m144k block. memory modes stratix iv trimatrix memory blocks allow you to implement fully synchronous sram memory in multiple modes of operation. m9k and m144k blocks do not support asynchronous memory (unregistered in puts). mlabs support asynchronous (flow-through) read operations. depending on which trimatrix memory block you target, you can use the following: ?single-port ram mode? on page 3?10 ?simple dual-port mode? on page 3?11 ?true dual-port mode? on page 3?14 ?shift-register mode? on page 3?16 ?rom mode? on page 3?17 ?fifo mode? on page 3?17 c when using the memory blocks in rom, si ngle-port, simple dual-port, or true dual-port mode, you can corrupt the memory contents if you violate the setup or hold-time on any of the memory block input registers. this applies to both read and write operations. figure 3?6. ecc block diagram of the m144k block data input 64 64 64 872 secded encoder ram array 72 64 64 8 8 8 8 64 64 3 status flags data output secded encoder comparator error correction block error locator flag generator 3?10 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook december 2011 altera corporation volume 1 single-port ram mode all trimatrix memory blocks support single-port mode. single-port mode allows you to do either one-read or one-write operatio n at a time. simultaneous reads and writes are not supported in single-port mode. figure 3?7 shows the single-port ram configuration. during a write operation, ram output be havior is configurable. if you use the read-enable signal and perform a write oper ation with read enable de-activated, the ram outputs retain the values they held duri ng the most recent active read enable. if you activate read enable during a write operation, or if you are not using the read-enable signal at all, the ram outputs either show the ?new data? being written, the ?old data? at that address, or a ?don?t care? value. to choose the desired behavior, set the read-during-write behavior to either new data , old data , or don?t care in the ram megawizard plug-in manager in the quar tus ii software. for more information, refer to ?read-during-write behavior? on page 3?19 . table 3?4 lists the possible port width configura tions for trimatrix memory blocks in single-port mode. figure 3?7. single-port ram (1) note to figure 3?7 : (1) you can implement two single-port memo ry blocks in a single m9k or m144k bl ock. for more information, refer to ?packed mode support? on page 3?5 . table 3?4. port width configurations for mlabs, m9k, and m144k blocks (single-port mode) mlabs m9k blocks m144k blocks port width configurations 648 649 64 10 32 16 32 18 32 20 8k 1 4k 2 2k 4 1k 8 1k 9 512 16 512 18 256 32 256 36 16k 8 16k 9 8k 16 8k 18 4k 32 4k 36 2k 64 2k 72 data[ ] address[ ] w ren b yteena[] addressstall inclock clockena rden aclr o u tclock q [] chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?11 memory modes december 2011 altera corporation stratix iv device handbook volume 1 figure 3?8 shows timing waveforms for read and write operations in single-port mode with unregistered outputs. register ing the ram?s outputs simply delays the q output by one clock cycle. simple dual-port mode all trimatrix memory blocks support simple dual-port mode. simple dual-port mode allows you to perform one read and one write operation to different locations at the same time. write operation happens on port a; read operation happens on port b. figure 3?9 shows a simple dual-port configuration. simple dual-port mode supports different read and write data widths (mixed-width support). table 3?5 lists the mixed width configurations for m9k blocks in simple dual-port mode. mlabs do not have native support for mixed-width operation. the quartus ii software implements mixed-wi dth memories in mlabs by using more than one mlab. figure 3?8. timing waveform for read-write operations (single-port mode) clk_a wrena rdena address a0 a1 bytenna 01 10 00 11 data_a a123 b456 c789 dddd eeee ffff q_a (asyn) a0 (old data) a1 (old data) dddd eeee b423 d old d old 23 figure 3?9. stratix iv simple dual-port memory (1) note to figure 3?9 : (1) simple dual-port ram supports input/output clock mode in addition to read/write clock mode. data[ ] w raddress[ ] w ren b yteena[] w r_addressstall w rclock w rclocken aclr rdaddress[ ] rden q [ ] rd_addressstall rdclock rdclocken ecc_stat u s table 3?5. m9k block mixed-width configurations (simple dual-port mode) (part 1 of 2) read port write port 8k1 4k2 2k4 1k8 51216 25632 1k9 51218 25636 8k1 yyyy y y ?? ? 4k2 yyyy y y ?? ? 2k4 yyyy y y ?? ? 3?12 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook december 2011 altera corporation volume 1 table 3?6 lists the mixed-width configurations for m144k blocks in simple dual-port mode. in simple dual-port mode, m9k and m144k bl ocks support separate write-enable and read-enable signals. you can save power by keeping the read-enable signal low (inactive) when not reading. read-during-write operations to the same address can either output a ?don?t care? value or ?old data? value. to choose the desired behavior, set the read-during-write behavior to either don?t care or old data in the ram megawizard plug-in manager in the quartus ii software. for more information, refer to ?read-during-write behavior? on page 3?19 . mlabs only support a write-enable signal. for mlabs, you can set the same-port read-during-write behavior to don?t care and the mixed-port read-during-write behavior to either don?t care or old data . the available choices depend on the configuration of the mlab. there is no ?new data? option for mlabs. 1k8 yyyy y y ?? ? 51216 yyyy y y ?? ? 25632 yyyy y y ?? ? 1k9 ???? ? ? y y y 51218 ???? ? ? y y y 25636 ???? ? ? y y y table 3?5. m9k block mixed-width configurations (simple dual-port mode) (part 2 of 2) read port write port 8k1 4k2 2k4 1k8 51216 25632 1k9 51218 25636 table 3?6. m144k block mixed-width configurations (simple dual-port mode) read port write port 16k 8 8k 16 4k 32 2k 64 16k 9 8k 18 4k 36 2k 72 16k8 yyyy ???? 8k16 yyyy ???? 4k32 yyyy ???? 2k64 yyyy ???? 16k9 ???? yyyy 8k18 ???? yyyy 4k36 ???? yyyy 2k72 ???? yyyy chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?13 memory modes december 2011 altera corporation stratix iv device handbook volume 1 figure 3?10 shows timing waveforms for read and write operations in simple dual-port mode with unregistered outp uts. registering the ram outputs simply delays the q output by one clock cycle. figure 3?11 shows timing waveforms for read and write operations in mixed-port mode with unregistered outputs. figure 3?10. simple dual-port timing waveforms wrclock wren wraddress rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden rdaddress bn b0 b1 b2 b3 doutn-1 doutn dout0 din-1 din din4 din5 din6 data figure 3?11. mixed-port read-during-write timing waveforms wrclock wren wraddress rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden rdaddress bn b0 b1 b2 b3 doutn-1 doutn dout0 din-1 din din4 din5 din6 data 3?14 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook december 2011 altera corporation volume 1 true dual-port mode stratix iv m9k and m144k blocks support true dual-port mode. sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 3?12 shows the true dual-port ram configuration. the widest bit configuration of the m9k and m144k blocks in true dual-port mode is as follows: m9k: 512 16-bit (or 512 18-bit with parity) m144k: 4k 32-bit (or 4k 36-bit with parity) wider configurations are unavailable beca use the number of output drivers is equivalent to the maximum bit width of th e respective memory block. because true dual-port ram has outputs on two ports, it s maximum width equals half of the total number of output drivers. table 3?7 lists the possible m9k block mixed-port width configurations in true dual-port mode. figure 3?12. stratix iv true dual-port memory (1) note to figure 3?12 : (1) true dual-port memory supports input/output clock mode in addition to independent clock mode. table 3?7. m9k block mixed-width configuration (true dual-port mode) read port write port 8k 1 4k 2 2k 4 1k 8 512 16 1k 9 512 18 8k1 yyyyy?? 4k2 yyyyy?? 2k4 yyyyy?? 1k8 yyyyy?? 512 16 y y y y y ? ? 1k9 ?????yy 512 18 ? ? ? ? ? y y data_a[ ] address_a[ ] w ren_a b yteena_a[] addressstall_a clock_a rden_a aclr_a q _a[] data_ b [ ] address_ b [] w ren_ b b yteena_ b [] addressstall_ b clock_ b rden_ b aclr_ b q _ b [] chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?15 memory modes december 2011 altera corporation stratix iv device handbook volume 1 table 3?8 lists the possible m144k block mixed-port width configurations in true dual-port mode. in true dual-port mode, m9k and m144k bl ocks support separate write-enable and read-enable signals. you can save power by keeping the read-enable signal low (inactive) when not reading. read-during-write operations to the same address can either output ?new data? at that location or ?old data?. to choose the desired behavior, set the read-during- write behavior to either new data or old data in the ram megawizard plug-in manager in the quar tus ii software. for more information, refer to ?read-during-write behavior? on page 3?19 . in true dual-port mode, you can access any memory location at any time from either port. when accessing the same memory location from both ports, you must avoid possible write conflicts. a write conflict happens when you attempt to write to the same address location from both ports at the same time. this results in unknown data being stored to that address location. no conf lict resolution circuitry is built into the stratix iv trimatrix memory blocks. you must handle address conflicts external to the ram block. figure 3?13 shows true dual-port timing waveform s for the write operation at port a and the read operation at port b, with the read-during-write behavior set to new data . registering the ram?s outputs simply delays the q outputs by one clock cycle. table 3?8. m144k block mixed-width configurations (true dual-port mode) read port write port 16k 8 8k 16 4k 32 16k 9 8k 18 4k 36 16k 8 y y y ? ? ? 8k16 y y y ??? 4k32 y y y ??? 16k 9 ? ? ? y y y 8k18 ???yyy 4k36 ???yyy figure 3?13. true dual-port timing waveform clk_a w ren_a address_a clk_ b an-1 an a0 a1 a2 a3 a4 a5 a6 q _ b (asynch) w ren_ b address_ b b n b 0 b 1 b 2 b 3 do u tn-1 do u tn do u t0 q _a (asynch) din-1 din din4 din5 din6 data_a din-1 din do u t0 do u t1 do u t2 do u t3 din4 din5 do u t2 do u t1 3?16 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook december 2011 altera corporation volume 1 shift-register mode all stratix iv memory blocks support shift register mode. embedded memory block configurations can implement shift registers for digital signal processing (dsp) applications, such as finite impulse response (fir) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flipflops that quickly exhaust many logic cells for large shift registers. a more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources. the size of a shift register ( w m n ) is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). you can cascade memory blocks to implement larger shift registers. figure 3?14 shows the trimatrix memory block in shift-register mode. figure 3?14. shift-register memory configuration w w x m x n shift register m-bit shift register m-bit shift register m-bit shift register m-bit shift register w w w w w w w n number of taps chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?17 clocking modes december 2011 altera corporation stratix iv device handbook volume 1 rom mode all stratix iv trimatrix memory blocks support rom mode. a .mif file initializes the rom contents of these blocks. the address lines of the rom are registered on m9k and m144k blocks, but can be unregistered on mlabs. the outputs can be registered or unregistered. output registers can be asynchronously cleared. the rom read operation is identical to the read operat ion in the single-port ram configuration. fifo mode all trimatrix memory blocks support fifo mode. mlabs are ideal for designs with many small, shallow fifo buffers. to impl ement fifo buffers in your design, use the quartus ii software fifo megawizard plug-in manager. both single- and dual-clock (asynchronous) fifo buffers are supported. f for more information about implementing fifo buffers, refer to the scfifo and dcfifo megafunctions user guide . 1 mlabs do not support mixed-width fifo mode. clocking modes stratix iv trimatrix memory blocks support the following clocking modes: ?independent clock mode? on page 3?18 ?input/output clock mode? on page 3?18 ?read/write clock mode? on page 3?18 ?single clock mode? on page 3?18 c violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. table 3?9 lists which clocking mode/memory mode combinations are supported. table 3?9. trimatrix memory clock modes clocking mode true dual-port mode simple dual-port mode single-port mode rom mode fifo mode independent y ? ? y ? input/output y y y y ? read/write ? y ? ? y single clock y y y y y 3?18 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook december 2011 altera corporation volume 1 independent clock mode stratix iv trimatrix memory blocks can im plement independent clock mode for true dual-port memories. in this mode, a separate clock is available for each port (clock a and clock b). clock a controls all register s on the port a side; clock b controls all registers on the port b side. each port also supports independent clock enables for both port a and port b registers, respecti vely. asynchronous clears are supported only for output latches and output registers on both ports. input/output clock mode stratix iv trimatrix memory blocks can impl ement input/output clock mode for true dual-port and simple dual-port memories. in this mode, an input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. an output clock controls the data output registers. asynchronous clears are availabl e on output latches and output registers only. read/write clock mode stratix iv trimatrix memory blocks can implement read/write clock mode for simple dual-port memories. in this mode, a write clock controls the data-input, write-address, and write-enable registers. similarly, a read clock controls the data-output, read-address, and read-enable registers. the memory blocks support independent clock enables for both read and write clocks. asynchronous clears are available on data output latches and registers only. when using read/write clock mode, if you perform a simultaneous read/write to the same address location, the output read data is unknown. if you require the output data to be a known value, use either sing le-clock mode or input/output clock mode and choose the appropriate read-during-write behavior in the megawizard plug-in manager. single clock mode stratix iv trimatrix memory blocks can implement single-clock mode for true dual-port, simple dual-port, and single-por t memories. in this mode, a single clock, together with a clock enable, is used to control all registers of the memory block. asynchronous clears are available on ou tput latches and output registers only. design considerations this section describes guidelines for designing with trimatrix memory blocks. selecting trimatrix memory blocks the quartus ii software automatically pa rtitions user-defined memory into embedded memory blocks by taking into account both speed and size constraints placed on your design. for example, the quartus ii software may spread memory out across multiple memory blocks when resources are available to increase the performance of the design. you can manually assign memory to a specific block size using the ram megawizard plug-in manager. chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?19 design considerations december 2011 altera corporation stratix iv device handbook volume 1 mlabs can implement single-port sram through emulation using the quartus ii software. emulation results in minimal additional logic resources being used. because of the dual-purpose architecture of the ml ab, it only has data input registers and output registers in the block. mlabs gain input address registers and additional data output registers from alms. f for more information about register packing, refer to the logic array blocks and adaptive logic modules in stratix iv devices chapter. conflict resolution when using memory blocks in true dual-port mode, it is possible to attempt two write operations to the same memory location (a ddress). because no conflict resolution circuitry is built into the memory blocks, this results in unknown data being written to that location. therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. read-during-write behavior you can customize the read-during-write beha vior of the stratix iv trimatrix memory blocks to suit your design needs. two types of read-during-write operations are available: same port and mixed port. figure 3?15 shows the difference between the two types. same-port read-during-write mode this mode applies to either a single-port ram or the same port of a true dual-port ram. for mlabs, the output of the mlabs can only be set to don?t care in same-port read-during-write mode. in this mode, the output of the mlabs is unknown during a write cycle. there is a window near the fa lling edge of the clock during which the output is unknown. prior to that window, ?o ld data? is read out; after that window, ?new data? is seen at the output. figure 3?15. stratix iv read-during-write data flow port a data in port b data in port a data out port b data out mixed-port data flow same-port data flow 3?20 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook december 2011 altera corporation volume 1 figure 3?16 shows sample functional waveforms of same-port read-during-write behavior in don?t care mode for mlabs. for m9k and m144k memory blocks, three ou tput choices are available in same-port read-during-write mode: ?new data? (or flow -through) or ?old data?. in new data mode, the ?new data? is available on the risi ng edge of the same clock cycle on which it was written. in old data mode, the ram outputs reflect the ?old data? at that address before the write operation proceeds. in don?t care mode, the ram outputs ?unknown values? for a read-during-write operation. figure 3?17 shows sample functional waveforms of same-port read-during-write behavior in new data mode for m9k and m144k blocks. figure 3?16. mlabs same-port read-during write: don?t care mode figure 3?17. m9k and m144k blocks same-port read-during-write: new data mode clk_a wrena data_in address a1 q(unregistered) a0(old data) a2 ffff aaaa xxxx xx ffff aaaa a1(old data) a2(old data) q(registered) ffff aaaa a0 xx xx xx clk_a wrena rdena address 0a 0b bytenna 01 10 00 11 data_a a123 b456 c789 dddd eeee ffff q_a (asyn) xx23 b423 b423 dddd eeee ffff chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?21 design considerations december 2011 altera corporation stratix iv device handbook volume 1 figure 3?18 shows sample functional waveforms of same-port read-during-write behavior in old data mode for m9k and m144k blocks. mixed-port read-during-write mode this mode applies to a ram in simple or true dual-port mode that has one port reading from and the other port writing to the same address location with the same clock. in this mode, you have two output choices if you use the output register: ?old data,? or ?don?t care?. with mlabs, you also have the output register ?new data.? in old data mode, a read-during-write operation to different ports causes the ram outputs to reflect the ?old data? at that address location. in don?t care mode, the same operation results in a ?don?t care? or ?unknown? value on the ram outputs. f read-during-write behavior is controlled with the ram megawizard plug-in manager. for more information, refer to the internal memory (ram and rom) user guide . figure 3?19 shows a sample functional waveform of mixed-port read-during-write behavior for old data mode in mlabs. figure 3?18. m9k and m144k blocks same-port read-during-write: old data mode clk_a wrena rdena address a0 a1 bytenna 01 10 00 11 data_a a123 b456 c789 dddd eeee ffff q_a (asyn) a0 (old data) a1 (old data) dddd eeee b423 d old d old 23 figure 3?19. mlabs mixed-port read-during-write: old data mode clk_a wrena data_in wraddress a1 byteena_a q_b(registered) a0 rdaddress a1 a0 aaaa bbbb cccc dddd eeee ffff a0 (old data) a1 (old data) dddd aabb aaaa 11 01 10 11 01 10 ddee 3?22 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook december 2011 altera corporation volume 1 figure 3?20 shows a sample functional waveform of mixed-port read-during-write behavior for don?t care mode in mlabs. figure 3?21 shows a sample functional waveform of mixed-port read-during-write behavior for old data mode in m9k and m144k blocks. figure 3?20. mlabs mixed-port read-during-write: don?t care mode figure 3?21. m9k and m144k blocks mixed-port read-during write: old data mode clk_a wrena data_in wraddress a1 byteena_a q_b(registered) a0 rdaddress a1 a0 aaaa bbbb cccc dddd eeee ffff aaaa dddd ddee ccbb aabb 11 01 10 11 01 10 ffee clk_a&b wrena address_a bytenna 11 01 11 data_a q_b_(asyn) a0 (old data) a1 (old data) dddd eeee aabb aaaa a1 a0 aaaa bbbb cccc dddd eeee ffff a1 a0 address_b 10 rdenb chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?23 design considerations december 2011 altera corporation stratix iv device handbook volume 1 figure 3?22 shows a sample functional waveform of mixed-port read-during-write behavior for don?t care mode in m9k and m144k blocks. mixed-port read-during-write is not supported when two different clocks are used in a dual-port ram. the output value is un known during a dual-clock mixed-port read-during-write operation. power-up conditions and memory initialization m9k memory cells are initialized to all zeros through a default .mif file in the quartus ii software. however, you may specify your own initialization of the memory cells through a defined .mif file. m144k memory cells are not initialized and; therefore, come up in an undefined state. th is is to prevent the programming file from being too large. again, you may specify yo ur own initialization of the memory cells through a defined .mif file. mlabs power up to zero if output regi sters are used and power up reading the memory contents if output registers ar e not used. you must take this into consideration when designing logic that might evaluate the initial power-up values of the mlab memory block. for stratix iv devices, the quartus ii software initializes the ram cells to zero unless there is a .mif file specified. as mentioned, all memory blocks support initialization using a .mif file. you can create .mif files in the quartus ii software and specify their use with the ram megawizard plug-in manager when instantiating a memory in your design. even if a memory is pre-initialized (for example, using a .mif file), it still powers up with its outputs cleared. f for more information about .mif files, refer to the internal memory (ram and rom) user guide and the quartus ii handbook . figure 3?22. m9k and m144k blocks mixed-port read-during write: don?t care mode clk_a&b wrena rdenb address_a a0 a1 bytenna 11 01 10 11 data_a aaaa bbbb cccc dddd eeee ffff q_b_(asyn) xxxx (unknown data) address_b a0 a1 3?24 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook december 2011 altera corporation volume 1 power management stratix iv memory block clock-enables allow you to control clocking of each memory block to reduce ac power consumption. use the read-enable signal to ensure that read operations only occur when you need them to. if your design does not need read-during-write, you can reduce your power consumption by de-asserting the read-enable signal during write operat ions, or any period when no memory operations occur. the quartus ii software automatically pl aces any unused memory blocks in low-power mode to reduce static power. document revision history table 3?10 lists the revision history for this chapter. table 3?10. document revision history date version changes december 2011 3.3 updated the ?byte enable support? and ?mixed-port read-during-write mode? sections. updated table 3?1 . february 2011 3.2 updated the ?byte enable support? and ?power -up conditions and memory initialization? sections. applied new template. minor text edits. march 2010 3.1 updated the ?simple dual-port mode?, ?s ame-port read-during-write mode?, and ?mixed-port read-during-write mode? sections. updated figure 3?14. minor text edits. november 2009 3.0 updated table 3?2. updated the ?simple dual-port mode? section. minor text edits. updated graphics. june 2009 2.3 updated table 3?1 and figure 3?2. updated the ?introduction?, ?byte enable support?, ?mixed width support?, ?asynchronous clear?, ?single-port ram?, ?simple dual-port mode?, ?true dual-port mode?, ?fifo mode?, and ?read/write clock mode? sections. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. april 2009 2.2 updated table 3?2. march 2009 2.1 updated table 3?2. removed ?referenced documents? section. november 2008 2.0 updated ?power-up conditions and memory initialization? on page 3?20 may 2008 1.0 initial release. siv51004-3.1 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 4. dsp blocks in stratix iv devices this chapter describes how the stratix ? iv device digital signal processing (dsp) blocks are optimized to suppo rt dsp applications requiring high data throughput, such as finite impulse response (fir) filters, infinite impulse response (iir) filters, fast fourier transform (fft) functions, and encoders. you can configure the dsp blocks to implement one of several operational modes to suit your application. the built-in shift register chain, multipliers, and a dders/subtractors minimize the amount of external logic to implement these functions, resulting in efficient resource usage and improved performance and data th roughput for dsp applications. many complex systems, such as wimax, 3gpp wcdma, high-performance computing (hpc), voice over internet pr otocol (voip), h.264 video compression, medical imaging, and hdtv use sophisticated digital signal processing techniques, which typically require a large number of mathematical computations. stratix iv devices are ideally suited for these task s because the dsp blocks consist of a combination of dedicated elements that perf orm multiplication, ad dition, subtraction, accumulation, summation, and dynamic shift operations. along with the high-performance stratix iv soft logic fabric and trimatrix memory structures, you can configure dsp blocks to build sophisticated fixed-point and floating-point arithmetic fu nctions. these can be manipu lated easily to implement common, larger computationally intensive su bsystems such as fir filters, complex fir filters, iir filters, fft functions, and discrete cosine transform (dct) functions. this chapter contains the following sections: ?stratix iv dsp block overview? on page 4?2 ?stratix iv simplified dsp operation? on page 4?4 ?stratix iv operational modes overview? on page 4?8 ?stratix iv dsp block resource descriptions? on page 4?9 ?stratix iv operational mode descriptions? on page 4?15 ?software support? on page 4?35 february 2011 siv51004-3.1 4?2 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block overview stratix iv device handbook february 2011 altera corporation volume 1 stratix iv dsp block overview each stratix iv device has two to seven columns of dsp blocks that implement multiplication, multiply-a dd, multiply-accumulate (mac), and dynamic shift functions efficiently. architectural highli ghts of the stratix iv dsp block include: high-performance, power optimized, fully registered, and pipelined multiplication operations natively supported 9-, 12-, 18-, and 36-bit wordlengths natively supported 18-bit complex multiplications efficiently supported floating -point arithmetic formats (2 4-bit for single precision and 53-bit for double precision) signed and unsigned input support built-in addition, subtraction, and accumu lation units to combine multiplication results efficiently cascading 18-bit input bus to form the tap-delay line for filtering applications cascading 44-bit output bus to propagate ou tput results from one block to the next block without external logic support rich and flexible arithmetic rounding and saturation units efficient barrel shifter support loopback capability to support adaptive filtering table 4?1 lists the number of dsp blocks for the stratix iv device family. table 4?1. number of dsp blocks in stratix iv devices (part 1 of 2) family device dsp blocks independent input and output multiplication operators high-precision multiplier adder mode four multiplier adder mode 99 multipliers 12 12 multipliers 18 18 multipliers 18 18 complex 36 36 multipliers 18 36 multipliers 18 18 multipliers stratix iv e ep4se230 161 1,288 966 644 322 322 644 1288 ep4se360 130 1,040 780 520 260 260 520 1040 ep4se530 128 1,024 768 512 256 256 512 1024 ep4se820 120 960 720 480 240 240 480 960 stratix iv gx ep4sgx70 48 384 288 192 96 96 192 384 ep4sgx110 64 512 384 256 128 128 256 512 ep4sgx180 115 920 690 460 230 230 460 920 ep4sgx230 161 1,288 966 644 322 322 644 1288 ep4sgx290 104 832 624 416 208 208 416 832 ep4sgx360 (1) 130 1,040 780 520 260 260 520 1,040 ep4sgx360 (2) 128 1,024 768 512 256 256 512 1,024 ep4sgx530 128 1,024 768 512 256 256 512 1,024 chapter 4: dsp blocks in stratix iv devices 4?3 stratix iv dsp block overview february 2011 altera corporation stratix iv device handbook volume 1 table 4?1 shows that the largest stratix iv dsp- centric device provides up to 1288 18 18 multiplier functionality in the 36 36, complex 18 18, and summation modes. each dsp block occupies four labs in height and can be divided further into two half blocks that share some common clock sign als, but are for all common purposes identical in functionality. figure 4?1 shows the layout of each dsp block. stratix iv gt ep4s40g2 161 1,288 966 644 322 322 644 1,288 ep4s40g5 128 1,024 768 512 256 256 512 1,024 ep4s100g2 161 1,288 966 644 322 322 644 1,288 ep4s100g3 104 832 624 416 208 208 416 832 ep4s100g4 128 1,024 768 512 256 256 512 1,024 ep4s100g5 128 1,024 768 512 256 256 512 1,024 notes to table 4?1 : (1) this is applicable for all pa ckages in ep4sgx360 except f1932. (2) this is applicable for ep4sgx360f1932 only. table 4?1. number of dsp blocks in stratix iv devices (part 2 of 2) family device dsp blocks independent input and output multiplication operators high-precision multiplier adder mode four multiplier adder mode 99 multipliers 12 12 multipliers 18 18 multipliers 18 18 complex 36 36 multipliers 18 36 multipliers 18 18 multipliers figure 4?1. overview of dsp block signals 34 144 144 2 88 72 72 half-dsp block half-dsp block o u tp u t data o u tp u t data f u ll dsp block control inp u t data 4?4 chapter 4: dsp blocks in stratix iv devices stratix iv simplified dsp operation stratix iv device handbook february 2011 altera corporation volume 1 stratix iv simplified dsp operation in stratix iv devices, the fundamental bu ilding block is a pair of 18 18-bit multipliers followed by a first-stage 37-bi t addition/subtraction unit, as shown in equation 4?1 and figure 4?2 . 1 all signed numbers, input, and output data are represented in 2?s-complement format only. the structure shown in figure 4?2 is useful for building more complex structures, such as complex multipliers and 36 36 multipliers, as described in later sections. each stratix iv dsp block contains four two-multiplier adder units (2 two-multiplier adder units per half block). therefore, there are eight 18 18 multiplier functionalities per dsp block. equation 4?1. multiplier equation p[36..0] = a 0 [17..0] b 0 [17..0] a 1 [17..0] b 1 [17..0] figure 4?2. basic two-multiplier adder building block dq dq a0[17..0] a1[17..0] b1[17..0] b0[17..0] p[36..0] +/- chapter 4: dsp blocks in stratix iv devices 4?5 stratix iv simplifi ed dsp operation february 2011 altera corporation stratix iv device handbook volume 1 following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. you can configure the second-stage adders to provide the alternative functions per half block, as shown in equation 4?2 and equation 4?3 . in these equations, n denotes sample time and p[36..0] denotes the result from the two-multiplier adder units. equation 4?2 provides a sum of four 18 18-bit multiplication operations (four-multiplier adder). equation 4?3 provides a four 18 18-bit multiplication operation but with a maximum 44-bit accumu lation capability by feeding the output of the unit back to itself, as shown in figure 4?3 . depending on the mode you select, you can bypass all register stages except accumulation and loopback mode. in these two modes, one set of registers must be enabled. if the register set is not enabled, an infinite loop occurs. equation 4?2. four-multiplier adder equation z[37..0] = p 0 [36..0] + p 1 [36..0] equation 4?3. four-multiplier adder equation (44-bit accumulation) w n [43..0] = w n-1 [43..0] z n [37..0] figure 4?3. four-multiplier adder and accumulation capability 144 44 inp u t data inp u t register bank adder/ acc u m u lator o u tp u t register bank half-dsp block res u lt[] pipeline register bank 4?6 chapter 4: dsp blocks in stratix iv devices stratix iv simplified dsp operation stratix iv device handbook february 2011 altera corporation volume 1 to support commonly found fir-like structur es efficiently, a major addition to the dsp block in stratix iv devices is the ability to propagate the result of one half block to the next half block completely within the dsp block without additional soft logic overhead. this is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous half block with the 44-bit result of the current block. the 44-bit result is either fed to the next half block or out of the dsp block using the output register stage, as shown in figure 4?4 . detailed examples are described in later sections. the combination of a fast, low-latency four-multiplier adder unit and the ?chained cascade? capability of the ou tput chaining adder provides the optimal fir and vector multiplication capability. to support single-channel type fir filters efficiently, you can configure one of the multiplier input?s registers to form a ta p delay line input, saving resources and providing higher system performance. also shown in figure 4?4 is the optional rounding and saturation unit (rsu). this unit provides a rich set of commonly fo und arithmetic rounding and saturation functions used in signal processing. in addition to the independent multipliers and sum modes, you can use dsp blocks to perform shift operations. dsp blocks can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. figure 4?4. output cascading feature for fir structures 144 44 44 from pre v io u s half dsp block to n ext half dsp block inp u t data inp u t register bank adder/ acc u m u lator ro u nd/sat u rate o u tp u t register bank 44 half dsp block res u lt[] pipeline register bank chapter 4: dsp blocks in stratix iv devices 4?7 stratix iv simplifi ed dsp operation february 2011 altera corporation stratix iv device handbook volume 1 figure 4?5 shows a top-level view of the stratix iv dsp block. figure 4?6 on page 4?9 shows a more detailed top- level view of the dsp block. figure 4?5. stratix iv full dsp block inp u t register bank pipeline register bank adder/acc u m u lator o u tp u t m u ltiplexer ro u nd/sat u rate o u tp u t register bank from pre v io u s half dsp block to n ext half dsp block 44 44 inp u t data 144 inp u t register bank pipeline register bank adder/acc u m u lator o u tp u t m u ltiplexter ro u nd/sat u rate o u tp u t register bank inp u t data 144 top half dsp block bottom half dsp block res u lt[] res u lt[] 4?8 chapter 4: dsp blocks in stratix iv devices stratix iv operatio nal modes overview stratix iv device handbook february 2011 altera corporation volume 1 stratix iv operational modes overview you can use each stratix iv dsp block in one of five basic operational modes. table 4?2 lists the five basic operational modes and the number of multipliers that you can implement within a single dsp block, depending on the mode. the dsp block consists of two identical halv es (the top half and bottom half). each half has four 18 18 multipliers. the quartus ? ii software includes megafunctions used to control the mode of operation of the multipliers. after making the appropriate parameter settings using the megafunction?s megawizard ? plug-in manager, the quartus ii software automatically configures the dsp block. stratix iv dsp blocks can operate in differ ent modes simultaneously. each half block is fully independent except for the sharing of the three clock , ena , and aclr signals. for example, you can break down a single dsp block to operate a 9 9 multiplier in one half block and an 18 18 two-multiplier adder in the other half block. this increases dsp block resource efficiency and allows you to implement more multipliers within a stratix iv device. the quartus ii software automatically places multipliers that can share the same dsp block resources within the same block. table 4?2. stratix iv dsp block operation modes mode multiplier in width # of mults # per block signed or unsigned rnd, sat in shift register chainout adder 1st stage add/sub 2nd stage add/acc independent multiplier 9 bits 1 8 both no no no ? ? 12 bits 1 6 both no no no ? ? 18 bits 1 4 both yes yes no ? ? 36 bits 1 2 both no no no ? ? double 1 2 both no no no ? ? two-multiplier adder (1) 18 bits 2 4 signed (4) yes no no both ? four-multiplier adder 18 bits 4 2 both yes yes yes both add only multiply accumulate 18 bits 4 2 both yes yes yes both both shift (2) 36 bits (3) 1 2 both no no ? ? ? high precision multiplier adder 18 ? 36 2 2 both no no no ? add only notes to table 4?2 : (1) this mode also su pports loopback mode. in loopback mode , the number of loopb ack multipliers per dsp block is two. you can us e the remaining multipliers in regular two-multiplier adder mode. (2) dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, l ogical shift right, and rota tion operation. (3) dynamic shift mode operates on a 32-bit input vector but the multiplier width is configured as 36 bits. (4) unsigned value is also supported but you must ensu re that the result can be contained within 36 bits. chapter 4: dsp blocks in stratix iv devices 4?9 stratix iv dsp block resource descriptions february 2011 altera corporation stratix iv device handbook volume 1 stratix iv dsp block resource descriptions the dsp block consists of the following elements: input register bank four two-multiplier adders pipeline register bank two second-stage adders four rounding and saturation logic units second adder register and output register bank figure 4?6 shows a detailed overall architecture of the top half of the dsp block. table 4?9 on page 4?34 shows a list of dsp block dynamic signals. figure 4?6. half dsp block architecture notes to figure 4?6 : (1) block output for accumulator o verflow and saturate overflow. (2) block output for saturation overflow of chainout . (3) the chainin port must only be connected to chainout of the previous dsp blocks and must not be connected to general routings. chainin[ ] (3) scanina[ ] dataa_0[ ] data b _0[ ] dataa_1[ ] data b _1[ ] dataa_2[ ] data b _2[ ] dataa_3[ ] scano u ta chaino u t data b _3[ ] inp u t register bank first stage adder first stage adder pipeline register bank second stage adder/acc u m u lator first ro u nd/sat u rate second adder register bank chaino u t adder second ro u nd/sat u rate o u tp u t register bank shift/rotate res u lt[ ] clock[3..0] ena[3..0] alcr[3..0] zero_loop b ack acc u m_sload zero_chaino u t chaino u t_ro u nd chaino u t_sat u rate signa sign b o u tp u t_ro u nd o u tp u t_sat u rate rotate shift_right o v erflo w (1) chaino u t_sat_o v erflo w (2) half-dsp block loop b ack m u ltiplexer 4?10 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block resource descriptions stratix iv device handbook february 2011 altera corporation volume 1 input registers all of the dsp block registers are triggered by the positive edge of the clock signal and are cleared after power up. each multiplier operand can feed an input register or go directly to the multiplier, bypassing the input registers. the following dsp block signals control the input registers within the dsp block: clock[3..0] ena[3..0] aclr[3..0] every dsp block has nine 18-bit data input register banks per half dsp block. every half dsp block has the option to use the eight data register banks as inputs to the four multipliers. the special ninth register bank is a delay register required by modes that use both the cascade and chainout features of the dsp block. us e the ninth register bank to balance the latency requirements when using the chained cascade feature. chapter 4: dsp blocks in stratix iv devices 4?11 stratix iv dsp block resource descriptions february 2011 altera corporation stratix iv device handbook volume 1 a feature of the input register bank is to support a tap delay line. therefore, the top leg of the multiplier input (a) can be driven from general routing or from the cascade chain, as shown in figure 4?7 . table 4?9 on page 4?34 lists the dsp block dynamic signals. at compile time, you must select whether the a-input comes from general routing or from the cascade chain. in cascade mode , the dedicated shift outputs from one multiplier block and directly feeds the input registers of the adjacent multiplier below it (within the same half dsp block) or the first multiplier in the next half dsp block, to form an 8-tap shift register chain per dsp block. the dsp block can increase the length of the shift register chain by cascad ing to the lower dsp blocks. the dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular fpga routing resources. figure 4?7. input register of a half dsp block +/- +/- signa sign b clock[3..0] ena[3..0] aclr[3..0] scanina[17..0] dataa_0[17..0] loop b ack data b _0[17..0] dataa_1[17..0] data b _1[17..0] dataa_2[17..0] data b _2[17..0] dataa_3[17..0] data b _3[17..0] scano u ta delay register 4?12 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block resource descriptions stratix iv device handbook february 2011 altera corporation volume 1 shift registers are useful in dsp functions such as fir filters. when implementing 18 18 or smaller width multipliers, you do no t need external logic to create the shift register chain because the input shift registers are internal to the dsp block. this implementation significantly reduces the logical element (le) resources required, avoids routing congestion, and results in predictable timing. the first multiplier in every half dsp block (top- and bottom-half) in stratix iv devices has a multiplexer for the first multipli er b-input (lower-leg input) register to select between general routing and loopback, as shown in figure 4?6 on page 4?9 . in loopback mode, the most significant 18-b it registered outputs are connected as feedback to the multiplier input of the firs t top multiplier in each half dsp block. loopback modes are used by recursive filter s where the previous output is needed to compute the current output. loopback mode is described in ?two-multiplier adder sum mode? on page 4?22 . table 4?3 lists input register modes for the dsp block. multiplier and first-stage adder the multiplier stage natively supports 9 9, 12 12, 18 18, or 36 36 multipliers. other wordlengths are padded up to the ne arest appropriate native wordlength; for example, 16 16 would be padded up to us e 18 18. for more information, refer to ?independent multiplier modes? on page 4?15 . depending on the data width of the multiplier, a single dsp block can perf orm many multiplications in parallel. each multiplier operand can be a unique signed or unsigned number. two dynamic signals, signa and signb , control the representation of each operand, respectively. a logic 1 value on the signa/signb signal indicates that data a/data b is a signed number; a logic 0 value indicates an unsigned number. table 4?4 lists the sign of the multiplication result for the various operan d sign representations. the result of the multiplication is signed if any one of the operands is a signed value. table 4?3. input register modes register input mode (1) 99 1212 1818 3636 double parallel input y y y y y shift register input (2) ??y?? loopback input (3) ??y?? notes to table 4?3 : (1) multiplier operand input wordlengths are statically configured at compile time. (2) available only on the a-operand. (3) only one loopback input is allowed per half block. for more information, refer to figure 4?15 on page 4?24 . table 4?4. multiplier sign representation data a (signa value) data b (signb value) result unsigned (logic 0) unsigned (logic 0) unsigned unsigned (logic 0) signed (logic 1) signed signed (logic 1) unsigned (logic 0) signed signed (logic 1) signed (logic 1) signed chapter 4: dsp blocks in stratix iv devices 4?13 stratix iv dsp block resource descriptions february 2011 altera corporation stratix iv device handbook volume 1 each half block has its own signa and signb signal. therefore, all of the data a inputs feeding the same half dsp bloc k must have the same sign representation. similarly, all of the data b inputs feeding the same half dsp block must have the same sign representation. the multiplier offers full precision regardless of the sign representation in all operational modes exce pt for full precision 18 18 loopback and two-multiplier adder modes. for more information, refer to ?two-multiplier adder sum mode? on page 4?22 . 1 by default, when the signa and signb signals are unused, the quartus ii software sets the multiplier to perform unsigned multiplication. figure 4?6 on page 4?9 shows that the outputs of the multipliers are the only outputs that can feed into the first-stage adder. ther e are four first-stage adders in a dsp block (two adders per half dsp block). the first-stage adder block has the ability to perform addition and subtraction. the control signal for addition or subtraction is static and has to be configured after compile time. th e first-stage adders are used by the sum modes to compute the sum of two multipli ers, 18 18-complex multipliers, and to perform the first stage of a 36 36 multiply and shift operations. depending on your specifications, the output of the first-stage adde r has the option to feed into the pipeline registers, second-sta ge adder, rounding and saturation unit, or output registers. pipeline register stage figure 4?6 on page 4?9 shows that the output from the first-stage adder can either feed or bypass the pipeline registers. pipeline registers increase the dsp block?s maximum performance (at the expense of extra cycles of latency), especially when using the subsequent dsp block stages. pipeline registers split up the long signal path between the input registers/multiplier/first-stage adder and the second-stage adder/ round-and-saturation/output registers, creating two shorter paths. second-stage adder there are four individual 44-bit second-stage adders per dsp block (two adders per half dsp block). you can configure the second-stage adders as follows: the final stage of a 36-bit multiplier a sum of four (18 18) an accumulator (44-bits maximum) a chained output summati on (44-bits maximum) 1 you can use the chained-output adder at th e same time as a second-level adder in chained output summation mode. the output of the second-stage adder has the option to go into the rounding and saturation logic unit or the output register. 1 you cannot use the second-stage adder independently from the multiplier and first-stage adder. 4?14 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block resource descriptions stratix iv device handbook february 2011 altera corporation volume 1 rounding and saturation stage the rounding and saturation logic units are located at the output of the 44-bit second-stage adder (the rounding logic unit followed by the saturation logic unit). there are two rounding and saturation logic units per half dsp block. the input to the rounding and saturation logic unit can come from one of the following stages: output of the multiplier (independent multiply mode in 18 18) output of the first-stage adder (two-multiplier adder) output of the pipeline registers output of the second-stage adder (four-multiplier adder and multiply-accumulate mode in 18 18) these stages are described in ?stratix iv operational mode descriptions? on page 4?15 . the rounding and saturation logic unit is controlled by the dynamic rounding and saturate signals, respectively. a logic 1 value on the rounding and/or saturate signals enables the rounding and/or saturate logic unit, respectively. 1 you can use the rounding and saturation logic units together or independently. second adder and output registers the second adder register and output regist er banks are two banks of 44-bit registers that you can combine to form larger 72-bit banks to support 36 36 output results. the outputs of the different stages in the stratix iv devices are routed to the output registers through an output selection unit. depending on the operational mode of the dsp block, the output selection unit sele cts whether the outputs of the dsp blocks comes from the outputs of the multiplier bloc k, first-stage adder, pipeline registers, second-stage adder, or the rounding and sa turation logic unit. the output selection unit is set automatically by the software , based on the dsp block operational mode you specified, and has the option to either drive or bypass the output registers. the exception is when you use the block in shift mode, in which case you dynamically control the output-select multiplexer directly. when the dsp block is configured in chained cascaded output mode, both of the second-stage adders are used. use the fi rst one for performing a four-multiplier adder; use the second for the chainout adder. the outputs of the four-multiplier adder are routed to the second-stage adder registers before they enter the chainout adde r. the output of the chainout adder goes to the regular output register bank. depe nding on the configuration, you can route the chainout results to the input of the next half block?s chainout adder input or to the general fabric (functioning as regular output registers). for more information, refer to ?stratix iv operational mode descriptions? on page 4?15 . chapter 4: dsp blocks in stratix iv devices 4?15 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 the second-stage and output registers are tr iggered by the positive edge of the clock signal and are cleared after power up. th e following dsp block signals control the output registers within the dsp block: clock[3..0] ena[3..0] aclr[3..0] stratix iv operational mode descriptions this section contains an explanation of different operational modes in stratix iv devices. independent mu ltiplier modes in independent input and output multiplier mode, the dsp block performs individual multiplication operations fo r general-purpose multipliers. 9-, 12-, and 18-bit multiplier you can configure each dsp bl ock multiplier for 9-, 12-, or 18-bit multiplication. a single dsp block can support up to eight individual 9 9 multipliers, six individual 12 12 multipliers, or four individual 18 18 multipliers. for operand widths up to 9 bits, a 9 9 multiplier is implemented. for operand widths from 10 to 12 bits, a 12 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an 18 18 multiplier is implemented. this is done by the quartus ii software by zero-padding the lsbs. figure 4?8 , figure 4?9 , and figure 4?10 show the dsp block in the independent multiplier operation. table 4?9 on page 4?34 lists the dynamic signals for the dsp block. 4?16 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 figure 4?8. 18-bit independent multiplier mode shown for a half dsp block note to figure 4?8 : (1) block output for accu mulator overflow and saturate overflow. clock[3..0] ena[3..0] aclr[3..0] signa sign b o u tp u t_ro u nd o u tp u t_sat u rate o v erflo w (1) 36 36 dataa_0[17..0] data b _0[17..0] dataa_1[17..0] data b _1[17..0] half-dsp block inp u t register bank pipeline register bank ro u nd/sat u rate ro u nd/sat u rate o u tp u t register bank 1 8 1 8 1 8 1 8 res u lt_0[ ] res u lt_1[ ] chapter 4: dsp blocks in stratix iv devices 4?17 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 figure 4?9. 12-bit independent multiplier mode shown for a half dsp block 24 12 12 12 12 12 12 24 24 inp u t register bank pipeline register bank o u tp u t register bank clock[3..0] ena[3..0] aclr[3..0] signa sign b half-dsp block dataa_0[11..0] data b _0[11..0] dataa_1[11..0] data b _1[11..0] dataa_2[11..0] data b _2[11..0] res u lt_0[ ] res u lt_1[ ] res u lt_2[ ] 4?18 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 the multiplier operands can accept signed integers, unsigned integers, or a combination of both. you can change the signa and signb signals dynamically and can register the signals in the dsp block. additionally, the multiplier inputs and results can be registered independently. yo u can use the pipeline registers within the dsp block to pipeline the multiplier resu lt, increasing the performance of the dsp block. 1 the rounding and saturation logic unit is supported for 18-bit independent multiplier mode only. figure 4?10. 9-bit independent multiplier mode shown for a half block 1 8 9 9 9 9 1 8 9 9 1 8 9 9 1 8 inp u t register bank pipeline register bank o u tp u t register bank dataa_0[ 8 ..0] data b _0[ 8 ..0] dataa_1[ 8 ..0] data b _1[ 8 ..0] dataa_2[ 8 ..0] data b _2[ 8 ..0] dataa_3[ 8 ..0] data b _3[ 8 ..0] half-dsp block clock[3..0] ena[3..0] aclr[3..0] signa sign b res u lt_0[ ] res u lt_1[ ] res u lt_2[ ] res u lt_3[ ] chapter 4: dsp blocks in stratix iv devices 4?19 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 36-bit multiplier you can efficiently construct a 36 36 multip lier using four 18 18 multipliers. this simplification fits conveniently into one half dsp block and is implemented in the dsp block automatically by selecting 36 36 mode. stratix iv devices can have up to two 36-bit multipliers per dsp block (one 36-bit multiplier per half dsp block). the 36-bit multiplier is also under the independent multiplier mode but uses the entire half dsp block, including the dedicated hardware logic after the pipeline registers to implement the 36 36 bit multiplica tion operation, as shown in figure 4?11 . the 36-bit multiplier is useful for applications requiring more than 18-bit precision; for example, for the mantissa multiplication portion of single precision and extended single precision floating-poi nt arithmetic applications. figure 4?11. 36-bit independent multiplier mode shown for a half dsp block pipeline register bank input register bank output register bank half-dsp block dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] 72 clock[3..0] ena[3..0] aclr[3..0] signa signb + + + result[ ] 4?20 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 double multiplier you can configure the stratix iv dsp block to efficiently support a signed or unsigned 54 54-bit multiplier that is required to compute the mantissa portion of an ieee double-precision floating point multiplication. you can build a 54 54-bit multiplier using basic 18 18 multipliers, shifters, an d adders. in order to efficiently use the stratix iv dsp block?s built-in shifters and adders, a special double mode (partial 54 54 multiplier) is available that is a slight modification to the basic 36 36 multiplier mode, as shown in figure 4?12 and figure 4?13 . figure 4?12. double mode shown for a half dsp block pipeline register bank input register bank output register bank half-dsp block dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] 72 clock[3..0] ena[3..0] aclr[3..0] signa signb + + + result[ ] chapter 4: dsp blocks in stratix iv devices 4?21 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 figure 4?13. unsigned 54 54 multiplier for a half-dsp block shifters and adders double mode shifters and adders 36 x 36 mode + two multiplier adder mode final adder (implemented with alut logic) 36 55 72 108 result[ ] unsigned 54 x 54 multiplier "0" "0" dataa[53..36] dataa[53..36] dataa[53..36] datab[53..36] dataa[35..18] datab[53..36] dataa[17..0] datab[53..36] datab[35..18] datab[17..0] clock[3..0] ena[3..0] aclr[3..0] signa signb dataa[35..18] dataa[35..18] datab[35..18] datab[17..0] datab[17..0] dataa[17..0] datab[35..18] dataa[17..0] 4?22 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 two-multiplier adder sum mode in a two-multiplier adder configuration, the dsp block can implement four 18-bit two-multiplier adders (2 two-multiplier adders per half dsp block). you can configure the adders to take the sum or diff erence of two multiplier outputs. you must select summation or subtraction at compile time. the two-multiplier adder function is useful for applications such as ffts, complex fir, and iir filters. figure 4?14 on page 4?23 shows the dsp block configured in two-multiplier adder mode. loopback mode is the other sub-featur e of the two-multiplier adder mode. figure 4?15 on page 4?24 shows the dsp block configured in the loopback mode. this mode takes the 36-bit summation result of the two multipliers and feeds back the most significant 18-bits to the input. the lower 18-bits are discarded. you have the option to disable or zero-out the loopback data by using the dynamic zero_loopback signal. a logic 1 value on the zero_loopback signal selects the zeroed data or disables the looped back data, while a logic 0 selects the looped back data. 1 you must select the option to use loopback mode or the general two-multiplier adder mode at compile time. for two-multiplier adder mode, if all the inputs are full 18-bit and unsigned, the result requires 37 bits. as the output data width in two-multiplier adder mode is limited to 36 bits, this 37-bit output requirement is not allowed. any other combination that does not violate the 36-bit maximum result is permitted; for example, two 16 16 signed two-multiplier adders is valid. two-multiplier adder mode supports the rounding and saturation logic unit. you can use the pipeline registers an d output registers within the dsp block to pipeline the multiplier-adder result, increasing the performance of the dsp block. chapter 4: dsp blocks in stratix iv devices 4?23 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 figure 4?14. two-multiplier adder mode shown for a half dsp block note to figure 4?14 : (1) block output for accu mulator overflow and saturate overflow. inp u t register bank pipeline register bank ro u nd/sat u rate o u tp u t register bank clock[3..0] ena[3..0] aclr[3..0] signa sign b o u tp u t_ro u nd o u tp u t_sat u rate o v erflo w (1) res u lt[ ] + dataa_0[17..0] data b _0[17..0] dataa_1[17..0] data b _1[17..0] half-dsp block 4?24 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 18 x 18 complex multiply you can configure the dsp block to implement complex multipliers using two-multiplier adder mode. a single half dsp block can implement one 18-bit complex multiplier. equation 4?4 shows a complex multiplication. figure 4?15. loopback mode for a half dsp block note to figure 4?15 : (1) block output for accumulator o verflow and saturate overflow. inp u t register bank pipeline register bank ro u nd/sat u rate o u tp u t register bank dataa_0[17..0] data b _0[17..0] dataa_1[17..0] data b _1[17..0] zero_loop b ack clock[3..0] ena[3..0] aclr[3..0] signa sign b o u tp u t_ro u nd o u tp u t_sat u rate o v erflo w (1) res u lt[ ] + loop b ack half-dsp block equation 4?4. complex multiplication equation (a + jb) (c + jd) = ((a c) ? (b d)) + j((a d) + (b c)) chapter 4: dsp blocks in stratix iv devices 4?25 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 to implement this complex multiplication within the dsp block, the real part ((a c) ? (b d)) is implemented using two multipliers feeding one subtractor block while the imaginary part ((a d) + (b c)) is implemented using another two multipliers feeding an adder block. figure 4?16 shows an 18-bit complex multiplication. this mode automatically assumes all inputs are using signed numbers. figure 4?16. complex multiplier using two-multiplier adder mode inp u t register bank pipeline register bank o u tp u t register bank a x cb x d real part a x db x c imaginary part clock[3..0] ena[3..0] aclr[3..0] signa sign b a c b d half-dsp block 36 36 4?26 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 four-multiplier adder in the four-multiplier adder configuration shown in figure 4?17 , the dsp block can implement two four-multiplier adders (one four-multiplier adder per half dsp block). these modes are useful for implementing one-dimensional and two-dimensional filtering applications. the four-multiplier adder is performed in two addition stages. the outputs of two of the four multipliers are initially summed in the two first-stage adder blocks. the results of these two adder blocks are then summed in the second-stage adder block to produce the fi nal four-multiplier adder result, as shown by equation 4?2 on page 4?5 and equation 4?3 on page 4?5 . figure 4?17. four-multiplier adder mode shown for a half dsp block note to figure 4?17 : (1) block output for accumulator o verflow and saturate overflow. clock[3..0] ena[3..0] aclr[3..0] signa sign b o u tp u t_ro u nd o u tp u t_sat u rate o v erflo w (1) inp u t register bank pipeline register bank ro u nd/sat u rate o u tp u t register bank dataa_0[ ] data b _0[ ] dataa_1[ ] data b _1[ ] dataa_2[ ] data b _2[ ] dataa_3[ ] data b _3[ ] half-dsp block + + + res u lt[ ] chapter 4: dsp blocks in stratix iv devices 4?27 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 four-multiplier adder mode supports the rounding and saturation logic unit. you can use the pipeline registers an d output registers within the dsp block to pipeline the multiplier-adder result, increasing the performance of the dsp block. high-precision multiplier adder mode in a high-precision multiplier adder configuration, shown in figure 4?18 on page 4?28 , the dsp block can implement 2 two-multiplier adders, with multiplier precision of 18 x 36 (one two-multiplier adder per half dsp block). this mode is useful in filtering or fft applications where a data path greater than 18 bits is required, yet 18 bits is sufficient for the coefficient precision. this can occur where the data has a high dynamic range. if the coefficients are fi xed, as in fft and most filter applications, the precision of 18 bits provide a dynamic ra nge over 100 db, if the largest coefficient is normalized to the maxi mum 18-bit representation. in these situations, the data path can be up to 36 bits, allowing sufficient capacity for bit growth or gain changes in the signal source without loss of precision. this mode is also extremely useful in single precision block floating point applications. the high-precision multiplier adder is performed in two stages. the 18 36 multiply is divided into two 18 18 multipliers. the multiplier with the lsb of the data source is performed unsigned, while the multiplier with the msb of the data source can be signed or unsigned. the latter multiplier has its result left shifted by 18 bits prior to the first adder stage, creating an effective 18 x 36 multip lier. the results of these two adder blocks are then summed in the second stage adder block to produce the final result: z[54..0] = p 0 [53..0] + p 1 [53..0] where: p 0 = a[17..0] b[35..0] p 1 = c[17..0] d[35..0] 4?28 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 figure 4?18. high-precision multiplier adder configuration note to figure 4?18 : (1) block output for accumulator o verflow and saturate overflow. clock[3..0] ena[3..0] aclr[3..0] signa sign b o v erflo w (1) inp u t register bank pipeline register bank o u tp u t register bank dataa[0:17] p 0 p 1 dataa[0:17] datac[0:17] datac[0:17] datad[0:17] datad[1 8 :35] datab[0:17] <<1 8 <<1 8 datab[1 8 :35] half-dsp block + + + res u lt[ ] chapter 4: dsp blocks in stratix iv devices 4?29 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 multiply accumulate mode in multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. the output of the dsp block is looped back to the second-stage adder and added or subtracted with the two outputs of the first-stage adder block according to equation 4?3 on page 4?5 . figure 4?19 shows the dsp block configured to operate in multiply accumulate mode. a single dsp block can implement up to two independent 44-bit accumulators. figure 4?19. multiply accumulate mode shown for a half dsp block note to figure 4?19 : (1) block output for saturatio n overflow of chainout. clock[3..0] ena[3..0] aclr[3..0] signa sign b o u tp u t_ro u nd o u tp u t_sat u rate chaino u t_sat_o v erflo w (1) inp u t register bank pipeline register bank ro u nd/sat u rate o u tp u t register bank dataa_0[ ] data b _0[ ] dataa_1[ ] data b _1[ ] dataa_2[ ] data b _2[ ] dataa_3[ ] data b _3[ ] half-dsp block + + + res u lt[ ] acc u m_sload 44 second register bank 4?30 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 use the dynamic accum_sload control signal to clear the accumulation. a logic 1 value on the accum_sload signal synchronously loads the accumulator with the multiplier result only, while a logic 0 enables accumulation by adding or subtracting the output of the dsp block (accumulator fe edback) to the output of the multiplier and first-stage adder. 1 you must configure the control signal for th e accumulator and subtra ctor if static at compile time. this mode supports the rounding and saturation logic unit because it is configured as an 18-bit multiplier accumulator. you can use the pipeline registers and output registers within the dsp block to incr ease the performance of the dsp block. shift modes stratix iv devices support the following shift modes for 32-bit input only: arithmetic shift left, asl[n] arithmetic shift right, asr[32-n] logical shift left, lsl[n] logical shift right, lsr[32-n] 32-bit rotator or barrel shifter, rot[n] 1 you can switch between these modes using the dynamic rotate and shift control signals. you can use shift mode in a stratix iv device by using a soft embedded processor such as nios ? ii to perform the dynamic shift and rotate operation. figure 4?20 on page 4?31 shows the shift mode configuration. shift mode makes use of the available multip liers to logically or arithmetically shift left, right, or rotate the desired 32-bit data. you can configure the dsp block similar to the independent 36-bit multiplier mode to perform shift mode operations. arithmetic shift right requires a signed input vector. during an arithmetic shift right, the sign is extended to fill the msb of the 32-bit vector. the logical shift right uses an unsigned input vector. during a logical shift right, zeros are padded in the msbs, shifting the 32-bit vector to the right. the barrel shifter uses unsigned input vector and implements a rotation functi on on a 32-bit word length. two control signals, rotate and shift_right , together with the signa and signb signals, determine the shifting operation. table 4?5 on page 4?31 lists examples of shift operations. chapter 4: dsp blocks in stratix iv devices 4?31 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 figure 4?20. shift operation mode shown for a half dsp block clock[3..0] ena[3..0] aclr[3..0] signa sign b rotate shift_right inp u t register bank pipeline register bank o u tp u t register bank dataa_0[35..1 8 ] data b _0[35..1 8 ] dataa_0[17..0] data b _0[35..1 8 ] dataa_0[35..1 8 ] data b _0[17..0] dataa_0[17..0] data b _0[17..0] half-dsp block + + + res u lt[ ] 32 shift/rotate table 4?5. examples of shift operations example signa signb shift rotate a-input b-input result logical shift left lsl[n] unsigned unsigned 0 0 0xaabbccdd 0x0000100 0xbbccdd00 logical shift right lsr[32-n] unsigned unsigned 1 0 0xaabbccdd 0x0000100 0x000000aa arithmetic shift left asl[n] signed unsigned 0 0 0xaabbccdd 0x0000100 0xbbccdd00 arithmetic shift right asr[32-n] signed unsigned 1 0 0xaabbccdd 0x0000100 0xffffffaa rotation rot[n] unsigned unsigned 0 1 0xaabbccdd 0x0000100 0xbbccddaa 4?32 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 rounding and saturation mode rounding and saturation functions are often required in dsp arithmetic. use rounding to limit bit growth and its side effe cts; use saturation to reduce overflow and underflow side effects. two rounding modes are supported in stratix iv devices: round-to-nearest-integer mode round-to-nearest-even mode 1 you must select one of these two options at compile time. round-to-nearest-integer provides the bias ed rounding support and is the simplest form of rounding commonly used in ds p arithmetic. the round-to-nearest-even method provides unbiased rounding support and is used where dc offsets are a concern. table 4?6 lists how round-to-nearest-even works. table 4?7 lists examples of the difference between the two modes. in this example, a 6-bit input is rounded to 4 bits. the main difference between the two rounding options is when the residue bits are exactl y halfway between its nearest two integers and the lsb is zero (even). table 4?6. example of round-to-nearest-even mode 6- to 4-bits rounding odd/even (integer) fractional add to integer result 010111 x > 0.5 (11) 1 0110 001101 x < 0.5 (01) 0 0011 001010 even (0010) = 0.5 (10) 0 0010 001110 odd (0011) = 0.5 (10) 1 0100 110111 x > 0.5 (11) 1 1110 101101 x < 0.5 (01) 0 1011 110110 odd (1101) = 0.5 (10) 1 1110 110010 even (1100) = 0.5 (10) 0 1100 table 4?7. comparison of round-to-nearest-integer and round-to-nearest-even round-to-nearest-integer round-to-nearest-even 010111 ? 0110 010111 ? 0110 001101 ? 0011 001101 ? 0011 001010 ? 0011 001010 ? 0010 001110 ? 0100 001110 ? 0100 110111 ? 1110 110111 ? 1110 101101 ? 1011 101101 ? 1011 110110 ? 1110 110110 ? 1110 110010 ? 1101 110010 ? 1100 chapter 4: dsp blocks in stratix iv devices 4?33 stratix iv operational mode descriptions february 2011 altera corporation stratix iv device handbook volume 1 two saturation modes are supported in stratix iv: asymmetric saturation mode symmetric saturation mode 1 you must select one of the two options at compile time. in 2?s-complement format, the maximum nega tive number that can be represented is ?2 (n?1) , while the maximum positive number is 2 (n?1) ? 1. symmetrical saturation limits the maximum negative number to ?2 (n?1) + 1. for example, for 32 bits: asymmetric 32-bit saturation: max = 0x7fffffff, min = 0x80000000 symmetric 32-bit saturation: max = 0x7fffffff, min = 0x80000001 table 4?8 lists how saturation works. in this ex ample, a 44-bit input is saturated to 36-bits. stratix iv devices have up to 16 configurable bit positions out of the 44-bit bus ( [43:0] ) for the rounding and saturate logic unit, providing higher flexibility. these 16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as shown in figure 4?21 . 1 you must select the 16 configurab le bit positions at compile time. 1 for symmetric saturation, the rnd bit positi on is also used to determine where the lsp for the saturated data is located. table 4?8. examples of saturation 44- to 36-bits saturation symmetric sat result asymmetric sat result 5926ac01342h 7ffffffffh 7ffffffffh ada38d2210h 800000001h 800000000h figure 4?21. rounding and saturation locations 43 42 29 28 1 0 43 42 21 20 7 6 0 16 user defined sat positions (bit 43-28) 16 user defined rnd positions (bit 21-6) 4?34 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook february 2011 altera corporation volume 1 use the rounding and saturation function just described in regular supported multiplication operations, as specified in table 4?2 on page 4?8 . however, for accumulation-type operations, use the following convention: the functionality of the round logic unit is in the format of: result = rnd[ s (a b)], when used for an a ccumulation type of operation. likewise, the functionality of the satura tion logic unit is in the format of: result = sat[ s (a b)], when used for an accumulation type of operation. if you use both the rounding and saturation logic units for an accumulation type of operation, the format is: result = sat[rnd[ s (a b)]] dsp block control signals the stratix iv dsp block is configured using a set of static and dynamic signals. you can configure the dsp block dy namic signals. you can set the signals to toggle or not toggle at run time. table 4?9 lists the dynamic signals for the dsp block. table 4?9. dsp block dynamic signals (part 1 of 2) signal name function count signa signb signed/unsigned control for all multipliers and adders. signa for ?multiplicand? input bus to dataa[17:0] to each multiplier signb for ?multiplier? input bus datab[17:0] to each multiplier signa = 1, signb = 1 for signed-signed multiplication signa = 1, signb = 0 for signed-unsigned multiplication signa = 0, signb = 1 for unsigned-signed multiplication signa = 0, signb = 0 for unsigned-unsigned multiplication 2 output_round round control for the first stage round and saturation block. output_round = 1 for rounding on multiply output output_round = 0 for normal multiply output 1 chainout_round round control for the second stage round and saturation block. chainout_round = 1 for rounding multiply output chainout_round = 0 for normal multiply output 1 output_saturate saturation control for the first stage round and saturation block for q-format multiply. if you enable both rounding and saturation, saturation is done on the rounded result. output_saturate = 1 for saturation support output_saturate = 0 for no saturation support 1 chainout_saturate saturation control for the second stage round and saturation block for q-format multiply. if you enable both rounding and saturation, saturation is done on the rounded result. chainout_saturate = 1 for saturation support chainout_saturate = 0 for no saturation support 1 chapter 4: dsp blocks in stratix iv devices 4?35 software support february 2011 altera corporation stratix iv device handbook volume 1 software support altera provides two distinct methods fo r implementing various modes of the dsp block in a design?instantiation and infe rence. both methods use the following quartus ii megafunctions: lpm_mult altmult_add altmult_accum altfp_mult to use the dsp block, instantiate the me gafunctions in the quartus ii software. alternatively, with inference, create an hdl design and synthesize it using a third-party synthesis tool (such as leonardospectrum ? , synplify, or quartus ii native synthesis) that infers the a ppropriate megafunction by recognizing multipliers, multiplier adders, multiplier accumulators, and shift functions. using either method, the quartus ii software ma ps the functionality to the dsp blocks during compilation. f for instructions about using these megafunctions and the megawizard plug-in manager , refer to quartus ii software help. accum_sload dynamically specifies whether the accumulator value is zero. accum_sload = 0, accumulation input is from the output registers accum_sload = 1, accumulation input is set to zero 1 zero_chainout dynamically specifies whether the chainout value is zero. 1 zero_loopback dynamically specifies whether the loopback value is zero. 1 rotate rotate = 1, the rotation feature is enabled 1 shift_right shift_right = 1, the shift right feature is enabled 1 total signals per half block 11 clock0 clock1 clock2 clock3 dsp-block-wide clock signals. 4 ena0 ena1 ena2 ena3 input and pipeline register enable signals. 4 aclr0 aclr1 aclr2 aclr3 dsp block-wide asynchronous clear signals (active low). 4 total count per full block 34 table 4?9. dsp block dynamic signals (part 2 of 2) signal name function count 4?36 chapter 4: dsp blocks in stratix iv devices software support stratix iv device handbook february 2011 altera corporation volume 1 f for more information, refer to the ?synthesis? section in volume 1 of the quartus ii handbook . document revision history table 4?10 lists the revision history for this chapter. table 4?10. document revision history date version changes february 2011 3.1 applied new template. minor text edits. november 2009 3.0 updated table 4?1. updated ?stratix iv simplified dsp operation? section. updated graphics. minor text edits. june 2009 2.3 added an introductory paragraph to increase search ability. removed the conclusion section. april 2009 2.2 updated table 4?1. march 2009 2.1 updated table 4?1. removed ?referenced documents? section. november 2008 2.0 updated table 4?2. updated figure 4?16. updated figure 4?18. may 2008 1.0 initial release. siv51005-3.4 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 september 2012 feedback subscribe iso 9001:2008 registered 5. clock networks and plls in stratix iv devices this chapter describes the hierarchical cloc k networks and phase-locked loops (plls) which have advanced features in stratix ? iv devices. it includes details about the ability to reconfigure the pll counter clock frequency and phase shift in real time, allowing you to sweep pll output frequencies and dynamically adjust the output clock phase shift. the quartus ? ii software enables the plls and their features without external devices. the following sections describe the stratix iv clock networks and plls in detail: ?clock networks in stratix iv devices? on page 5?1 ?plls in stratix iv devices? on page 5?19 clock networks in stratix iv devices the global clock networks (gclks), region al clock networks (rclks), and periphery clock networks (pclks) available in stratix iv devices are organized into hierarchical clock structures that provide up to 236 unique clock domains (16 gclks + 88 rclks + 132 pclks) within the stratix iv device and allow up to 71 unique gclk, rclk, and pclk clock sources (16 gclks + 22 rclks + 33 pclks) per device quadrant. table 5?1 lists the clock resources available in stratix iv devices. table 5?1. clock resources in stratix iv devices (part 1 of 2) clock resource number of resources available source of clock resource clock input pins 32 single-ended (16 differential) clk[0..15]p and clk[0..15]n pins gclk networks 16 clk[0..15]p and clk[0..15]n pins, pll clock outputs, and logic array rclk networks 64/88 (1) clk[0..15]p and clk[0..15]n pins, pll clock outputs, and logic array pclk networks 56/88/112/132 (33 per device quadrant) (2) dpa clock outputs, pld-transceiver interface clocks, horizontal i/o pins, and logic array gclks/rclks per quadrant 32/38 (3) 16 gclks + 16 rclks 16 gclks + 22 rclks september 2012 siv51005-3.4 5?2 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 stratix iv devices have up to 32 dedicated single-ended clock pins or 16 dedicated differential clock pins ( clk[0..15]p and clk[0..15]n ) that can drive either the gclk or rclk networks. these clock pins are arra nged on the four sides of the stratix iv device, as shown in figure 5?1 through figure 5?4 on page 5?5 . f for more information about how to connect the clock input pins, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . gclks/rclks per device 80/104 (4) 16 gclks + 64 rclks 16 gclks + 88 rclks notes to table 5?1 : (1) there are 64 rclks in the ep4s40g2, ep4s100g2, ep4se230, ep 4sgx70, ep4sgx110, ep4sgx180, a nd ep4sgx230 devices. there are 88 rclks in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4se820 , ep4sgx290, ep4sgx360, and ep4sgx530 devices. (2) there are 56 pclks in the ep4sgx70, and ep4sgx110 devices. there are 88 pclks in th e ep4s40g2, ep4s100g2, ep4se230, ep4se360 , ep4sgx180, ep4sgx230, ep4sgx290, and ep 4sgx360 devices. there are 112 pclks in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se530 and ep4sgx530 devices. there are 132 pclks in the ep4se820 device. (3) there are 32 gclks/rclks per quadrant in the ep4s40g2, ep4s10 0g2, ep4se230, ep4sgx70, ep4sgx 110, ep4sgx180, and ep4sgx230 devices. there are 38 gclks/rclks per quadran t in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4se820, ep4sgx290, ep4sgx360, and ep4sgx530 devices. (4) there are 80 gclks/rclks per entire device in the ep4s40g2, ep 4s100g2, ep4se230, ep4sgx70, ep4s gx110, ep4sgx180, and ep4sgx2 30 devices. there are 104 gclks/rclks per enti re device in the ep4s 40g5, ep4s100g3, ep4s100g4, ep 4s100g5, ep4se36 0, ep4se530, ep4se820, ep4sgx290, ep4sgx360, and ep4sgx530 devices. table 5?1. clock resources in stratix iv devices (part 2 of 2) clock resource number of resources available source of clock resource chapter 5: clock networks and plls in stratix iv devices 5?3 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 global clock networks stratix iv devices provide up to 16 gclk s that can drive throughout the device, serving as low-skew clock sources for func tional blocks such as adaptive logic modules (alms), digital signal processing (dsp) blocks, trimatrix memory blocks, and plls. stratix iv device i/o elements (ioes) and internal logic can also drive gclks to create internally generated glob al clocks and other high fan-out control signals; for example, synchronous or as ynchronous clears and clock enables. figure 5?1 shows the clk pins and plls that can drive the gclk networks in stratix iv devices. figure 5?1. gclk networks t1 t2 l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 gclk[0..3] gclk[4..7] gclk[8..11] gclk[12..15] clk[12..15] clk[4..7] clk[0..3] clk[8..11] 5?4 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 regional clock networks rclk networks only pertain to the quadrant they drive into. rclk networks provide the lowest clock delay and skew for logic contained within a single device quadrant. the stratix iv device ioes and internal logic within a given quadrant can also drive rclks to create internally generated region al clocks and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables. figure 5?2 through figure 5?4 on page 5?5 show the clk pins and plls that can drive the rclk networks in stratix iv devices. figure 5?2. rclk networks (ep4se230, ep4sgx70, and ep4sgx110 devices) (1) note to figure 5?2 : (1) a maximum of four signals from the core can drive into each group of rclks. for example, only four core signals can drive in to rclk[0..5] and another four core signals can drive into rclk[54..63] at any one time. t1 b1 rclk[0..5] rclk[38..43] rclk[6..11] rclk[32..37] rclk[54..63] rclk[44..53] rclk[12..21] rclk[22..31] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l2 r2 chapter 5: clock networks and plls in stratix iv devices 5?5 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 figure 5?3. rclk networks (ep4s40g2, ep4s100g2, ep4sgx180, and ep4sgx230 devices) (1) note to figure 5?3 : (1) a maximum of four signals from the core can drive into each group of rclks. for example, only four core signals can drive in to rclk[0..5] and another four core signals can drive into rclk[54..63] at any one time. rclk[0..5] rclk[38..43] rclk[6..11] rclk[32..37] rclk[54..63] rclk[44..53] rclk[12..21] rclk[22..31] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 r3 r2 t2 t1 b2 b1 l3 l2 figure 5?4. rclk networks (ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4se820, ep4sgx290, ep4sgx360, and ep4sgx530 devices) (1) , (2) , (3) notes to figure 5?4 : (1) the corner rclk[64..87] can only be fed by their respective corner pll outputs. for more info rmation about connectivity, refer to table 5?6 on page 5?13 . (2) the ep4s40g5 and ep4se360 devices have up to eight plls. for more in formation about pll a vailability, refer to table 5?7 on page 5?19 . (3) a maximum of four signals from the core can drive into each group of rclks. for example, only four core signals can drive in to rclk[0..5] and another four core signals can drive into rclk[54..63] at any one time. rclk[0..5] rclk[38..43] rclk[6..11] rclk[32..37] rclk[64..69] rclk[70..75] rclk[82..87] rclk[76..81] rclk[54..63] rclk[44..53] rclk[12..21] rclk[22..31] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l3 r3 l2 r2 l4 r4 l1 r1 t2 t1 b2 b1 5?6 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 periphery clock networks pclk networks shown in figure 5?5 through figure 5?8 on page 5?8 are collections of individual clock networks driven from th e periphery of the stratix iv device. clock outputs from the dynamic phase aligner (dpa) block, programmable logic device (pld)-transceiver interface clocks, i/o pins, and internal logic can drive the pclk networks. pclks have higher skew when compared with gclk and rclk networks. you can use pclks for general purpose routing to drive signals into and out of the stratix iv device. figure 5?5. pclk networks (ep4sgx70 and ep4sgx110 devices) t1 b1 clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l2 r2 pclk[0..13] pclk[42..56] pclk[14..27] pclk[28..41] chapter 5: clock networks and plls in stratix iv devices 5?7 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 figure 5?6. pclk networks (ep4s40g2, ep4s100g2, ep4 se230, ep4se360, ep4sgx180, ep4sgx230, ep4sgx290, and ep4sgx360 devices) (1) note to figure 5?6 : (1) the ep4se230 device has four plls. the ep4sgx290 and ep4sgx360 devices have up to 12 plls. for more info rmation about pll av ailability, refer to table 5?7 on page 5?19 . t2 b2 t1 b1 pclk[77.. 8 7] clk[12..15] clk[4..7] clk[0..3] clk[ 8 ..11] q1 q2 q4 q3 l3 r3 l2 r2 pclk[0..10] pclk[11..21] pclk[66..76] pclk[22..32] pclk[55..65] pclk[33..43] pclk[44..54] figure 5?7. pclk networks (ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se530, and ep4sgx530 devices) (1) note to figure 5?7 : (1) the ep4s40g5 device has eight plls. for more information about pll availability, refer to table 5?7 on page 5?19 . q1 q2 q4 q3 pclk[0..13] pclk[98..111] pclk[84..97] pclk[14..27] pclk[28..41] pclk[42..55] pclk[70..83] pclk[56..69] t2 b2 t1 b1 clk[12..15] clk[4..7] clk[0..3] clk[8..11] l3 r3 l2 r2 l4 r4 l1 r1 5?8 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 figure 5?8. pclk networks (ep4se820 device) q1 q2 q4 q3 pclk[0..15] pclk[16..32] pclk[116..131] pclk[99..115] pclk[82..98] pclk[33..49] pclk[50..65] pclk[66..81] t2 b2 t1 b1 clk[12..15] clk[4..7] clk[0..3] clk[8..11] l3 r3 l2 r2 l4 r4 l1 r1 chapter 5: clock networks and plls in stratix iv devices 5?9 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 clock sources per quadrant there are 26 section clock (sclk) networks available in each spine clock that can drive six row clocks in each logic array block (lab) row, nine column i/o clocks, and three core reference clocks. the sclks are the clock resources to the core functional blocks, plls, and i/o interfaces of the device. figure 5?9 shows that the sclks can be driven by the gclk, rclk, pclk, or the pll feedback clock networks in each spine clock. 1 a spine clock is another layer of routing below the gclks, rclks, and pclks before each clock is connected to clock routing for each lab row. the settings for spine clocks are transparent to all users. the qu artus ii software automatically routes the spine clock based on the gclk, rclk, and pclks. clock regions stratix iv devices provide up to 104 distinct clock domains (16 gclks + 88 rclks) in the entire device. you can use these clock resources to form the following types of clock regions: entire device regional dual-regional to form the entire device clock region, a source (not necessarily a clock signal) drives a gclk network that can be routed through th e entire device. this clock region has the maximum delay when compared with other cl ock regions, but allows the signal to reach every destination within the device. this is a good option for routing global reset and clear signals or routing clocks throughout the device. figure 5?9. hierarchical clock networks per spine clock (1) notes to figure 5?9 : (1) the gclk, rclk, pclk, and pll feedback clocks share th e same routing to the sclks. the total number of clock resources must not exceed the sclk limits in each region to ensure successf ul design fitting in the quartus ii software. (2) there are up to 16 pclks that can drive the sclks in each sp ine clock in th e largest device. (3) there are up to 22 rclks that can drive the sclks in each spine clock in the largest device. (4) the pll feedback clock is the clock fr om the pll that drives into the sclks. (5) the column i/o clock is the clock that drives the column i/o core registers and i/o interfaces. (6) the core reference clock is the clock that feeds into th e pll as the pll reference clock. (7) the row clock is the clock source to the lab, me mory blocks, and row i/o in terfaces in the core row. sclk col u mn i/o clock (5) core reference clock (6) ro w clock (7) gclk rclk pll feed b ack clock (4) pclk 9 3 26 16 3 16 (2) 22 (3) 6 5?10 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 to form a rclk region, a source drives a single quadrant of the device. this clock region provides the lowest skew within a quadrant and is a good option if all the destinations are within a single device quadrant. to form a dual-regional clock region, a single source (a clock pin or pll output) generates a dual-regional clock by driving two rclk networks (one from each quadrant). this technique allows destinatio ns across two device quadrants to use the same low-skew clock. the routing of this signal on an entire side has approximately the same delay as a rclk region. internal logic can also drive a dual-regional clock network. corner pll outputs only span one quadrant, they cannot generate a dual-regional clock network. figure 5?10 shows the dual-regional clock region. clock network sources in stratix iv devices, clock input pins, pll outputs, and internal logic can drive the gclk and rclk networks. for connectivity between dedicated pins clk[0..15] and the gclk and rclk networks, refer to table 5?2 and table 5?3 on page 5?11 . dedicated clock input pins clock pins can be either differential clocks or single-ended clocks. stratix iv devices support 16 differential clock inputs or 32 single-ended clock inputs. you can also use dedicated clock input pins clk[15..0] for high fan-out control signals such as asynchronous clears, presets, and clock enables for protocol signals such as trdy and irdy for pcie through the gclk or rclk networks. labs you can drive each gclk and rclk network using lab-routing to enable internal logic to drive a high fan-out, low-skew signal. 1 stratix iv plls cannot be driven by intern ally generated gclks or rclks. the input clock to the pll has to come from dedicated clock input pins or pin/pll-fed gclks or rclks. figure 5?10. stratix iv dual-regional clock region clock pins or pll outputs can drive half of the device to create side-wide clocking regions for improved interface timing. chapter 5: clock networks and plls in stratix iv devices 5?11 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 pll clock outputs stratix iv plls can drive both gclk and rclk networks, as described in table 5?5 on page 5?13 and table 5?6 on page 5?13 . table 5?2 lists the connection between the dedi cated clock input pins and gclks. table 5?3 lists the connectivity between the dedicated clock input pins and rclks in stratix iv devices. a given clock input pin can drive two adjacent rclk networks to create a dual-regional clock network. table 5?2. clock input pin connectivity to the gclk networks clock resources clk (p/n pins) 0123456789101112131415 gclk0 y y y y ???????????? gclk1 y y y y ???????????? gclk2 y y y y ???????????? gclk3 y y y y ???????????? gclk4 ???? y y y y ???????? gclk5 ???? y y y y ???????? gclk6 ???? y y y y ???????? gclk7 ???? y y y y ???????? gclk8 ???????? yyyy ???? gclk9 ???????? yyyy ???? gclk10 ???????? yyyy ???? gclk11 ???????? yyyy ???? gclk12 ???????????? yyyy gclk13 ???????????? yyyy gclk14 ???????????? yyyy gclk15 ???????????? yyyy table 5?3. clock input pin connectivity to the rclk networks (part 1 of 2) clock resource clk (p/n pins) 0123456789101112131415 rclk [0, 4, 6, 10] y ??????????????? rclk [1, 5, 7, 11] ? y ?????????????? rclk [2, 8] ?? y ????????????? rclk [3, 9] ??? y ???????????? rclk [13, 17, 21, 23, 27, 31] ???? y ??????????? rclk [12, 16, 20, 22, 26, 30] ????? y ?????????? rclk [15, 19, 25, 29] ?????? y ????????? rclk [14, 18, 24, 28] ??????? y ???????? rclk [35, 41] ???????? y ??????? 5?12 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 clock input connections to the plls table 5?4 lists the dedicated clock input pi n connectivity to stratix iv plls. rclk [34, 40] ????????? y ?????? rclk [33, 37, 39, 43] ?????????? y ????? rclk [32, 36, 38, 42] ??????????? y ???? rclk [47, 51, 57, 61] ???????????? y ??? rclk [46, 50, 56, 60] ????????????? y ? ? rclk [45, 49, 53, 55, 59, 63] ??????????????y? rclk [44, 48, 52, 54, 58, 62] ???????????????y table 5?3. clock input pin connectivity to the rclk networks (part 2 of 2) clock resource clk (p/n pins) 0123456789101112131415 table 5?4. device plls and pll clock pin drivers (1) , (2) dedicated clock input pin clk (p/n pins) pll number l1 (3) l2 l3 l4 (3) b1 b2 r1 (3) r2 r3 r4 (3) t1 t2 clk0 y y y y ????? ??? clk1 y y y y ????? ??? clk2 y y y y ????? ??? clk3 y y y y ????? ??? clk4 ??? ? y y ??? ??? clk5 ??? ? y y ??? ??? clk6 ??? ? y y ??? ??? clk7 ??? ? y y ??? ??? clk8 ??? ? ?? y y y y ?? clk9 ??? ? ?? y y y y ?? clk10 ??? ? ?? y y y y ?? clk11 ??? ? ?? y y y y ?? clk12 ??? ? ????? ? y y clk13 ??? ? ????? ? y y clk14 ??? ? ????? ? y y clk15 ??? ? ????? ? y y notes to table 5?4 : (1) for single-ended clock inputs, only the clk<#>p pin has a dedicated connectio n to the pll. if you use the clk<#>n pin, a global clock is used. (2) for the availability of the clock input pins in each device density, refer to the ?stratix iv device pin-out files? section of the pin-out files for altera devices site. (3) these are non-compensated clock input paths. for the compensated input for these plls, use the corresponding pll_[l, r][1,4]_clk input pin. chapter 5: clock networks and plls in stratix iv devices 5?13 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 1 dedicated clock pins can drive plls over dedicated routing; they do not require the global or regional network. compensated inputs, which are a subset of dedicated clock pins, drive plls that can only compensate the input delay when a dedicated clock pin is in the same i/o bank as the pll used. clock output connections plls in stratix iv devices can drive up to 20 rclk networks and four gclk networks. for stratix iv pll connectivity to gclk networks, refer to table 5?5 . the quartus ii software automatically assigns pll clock outputs to rclk and gclk networks. table 5?5 lists how the pll clock outputs connect to the gclk networks. table 5?6 lists how the pll clock outputs connect to the rclk networks. table 5?5. stratix iv pll connectivity to the gclk networks (1) clock network pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 gclk0 y y y y ???????? gclk1 y y y y ???????? gclk2 y y y y ???????? gclk3 y y y y ???????? gclk4 ???? y y ?????? gclk5 ???? y y ?????? gclk6 ???? y y ?????? gclk7 ???? y y ?????? gclk8 ?????? y y y y ?? gclk9 ?????? y y y y ?? gclk10 ?????? y y y y ?? gclk11 ?????? y y y y ?? gclk12 ?????????? y y gclk13 ?????????? y y gclk14 ?????????? y y gclk15 ?????????? y y note to table 5?5 : (1) only pll counter outputs c0 - c3 can drive the gclk networks. table 5?6. stratix iv rclk outputs from the pll clock outputs (1) (part 1 of 2) clock resource pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 rclk[0..11] ? y y ????????? rclk[12..31] ???? y y ?????? rclk[32..43] ??????? y y ??? rclk[44..63] ?????????? y y 5?14 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 clock control block every gclk and rclk network has its own clock control block. the control block provides the following features: clock source selection (dynamic selection for gclks) global clock multiplexing clock power down (static or dy namic clock enable or disable) figure 5?11 and figure 5?12 show the gclk and rclk select blocks, respectively. you can select the clock source for the gc lk select block either statically or dynamically. you can statically select the cl ock source using a setting in the quartus ii software or you can dynamically select the clock source using internal logic to drive the multiplexer-select inputs. when select ing the clock source dynamically, you can select either pll outputs (such as c0 or c1 ) or a combination of clock pins or pll outputs. rclk[64..69] ??? y ???????? rclk[70..75] ????????? y ?? rclk[76..81] ?????? y ????? rclk[82..87] y ??????????? note to table 5?6 : (1) all pll counter outputs can drive the rclk networks. table 5?6. stratix iv rclk outputs from the pll clock outputs (1) (part 2 of 2) clock resource pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 figure 5?11. stratix iv gclk control block notes to figure 5?11 : (1) when the device is operati ng in user mode, you can dyna mically control the clock sele ct signals through internal logic. (2) when the device is operation in user mode, you can only set the clock select signals through a configuration file (sram object file [ .sof] or programmer object file [ .pof] ) and cannot be dyna mically controlled. clkp pins pll co u nter o u tp u ts internal logic static clock select (2) clkselect[1..0] thi s m u ltiplexe r su ppo r t s us e r -co n t r ollable dy n amic s witchi n g (1) 2 2 2 clkn pin ena b le/ disa b le gclk internal logic chapter 5: clock networks and plls in stratix iv devices 5?15 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 the mapping between the input clock pins, pll counter outputs, and clock control block inputs is as follows: inclk[0] and inclk[1] ?can be fed by any of the four dedicated clock pins on the same side of the stratix iv device inclk[2] ?can be fed by pll counters c0 and c2 from the two center plls on the same side of the stratix iv device inclk[3] ?can be fed by pll counters c1 and c3 from the two center plls on the same side of the stratix iv device the corner plls (l1, l4, r1, and r4) and the corresponding clock input pins ( pll_l1_clk and so forth) do not support dynamic selection for the gclk network. the clock source selection for the gclk and rclk networks from the corner plls (l1, l4, r1, and r4) and the corresponding clock input pins ( pll_l1_clk and so forth) are controlled statically using configuration bit settings in the configuration file ( .sof or .pof ) generated by the quartus ii software. you can only control the clock source select ion for the rclk select block statically using configuration bit settings in the configuration file ( .sof or .pof ) generated by the quartus ii software. you can power down the stratix iv clock networks using both static and dynamic approaches. when a clock network is powe red down, all the logic fed by the clock network is in off-state, thereby reducing the overall power consumption of the device. the unused gclk and rclk networks ar e automatically powered down through configuration bit settings in the configuration file ( .sof or .pof ) generated by the quartus ii software. the dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on the gclk and rclk networks, including dual-regional clock region s. this function is independent of the pll and is applied directly on the clock network, as shown in figure 5?11 and figure 5?12 . figure 5?12. rclk control block notes to figure 5?12 : (1) when the device is operation in user mode, you can only set the clock sele ct signals through a configuration file ( .sof or .pof ) and cannot be dynamically controlled. (2) the clkn pin is not a dedicated clock input when used as a single-ended pll clock input. clkp pin pll co u nter o u tp u ts internal logic clkn pin ena b le/ disa b le rclk internal logic static clock select (1) 2 (2) 5?16 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 you can set the input clock sources and the clkena signals for the gclk and rclk network multiplexers through the quar tus ii software using the altclkctrl megafunction. you can also enable or disable the dedicated external clock output pins using the altclkctrl megafunction. figure 5?13 shows the external pll output clock control block. 1 when using the altclkctrl megafunction to implement dynamic clock source selection, the inputs from the clock pins feed the inclk[0..1] ports of the multiplexer, while the pll outputs feed the inclk[2..3] ports. you can choose from among these inputs using the clkselect[1..0] signal. f for more information, refer to the clock control block (altclkctrl) megafunction user guide . figure 5?13. stratix iv external pll output clock control block notes to figure 5?13 : (1) when the device is operation in user mode, you can only set the clock sele ct signals through a configuration file ( .sof or .pof ) and cannot be dynamically controlled. (2) the clock control block feeds to a mult iplexer within the pll_<#>_clkout pin?s ioe. the pll_ <#> _clkout pin is a dual-purpose pin. theref ore, this multiplexer selects either an intern al signal or the output of the clock control block. pll co u nter o u tp u ts ena b le/ disa b le pll_<#>_clkout pin internal logic static clock select ioe (1) static clock select (1) internal logic (2) 7 or 10 chapter 5: clock networks and plls in stratix iv devices 5?17 clock networks in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 clock enable signals figure 5?14 shows how the clock enable and disabl e circuit of the clock control block is implemented in stratix iv devices. in stratix iv devices, the clkena signals are supported at the clock network level instead of at the pll output counter level. this allows you to gate off the clock even when you are not using a pll. you can also use the clkena signals to control the dedicated external clocks from the plls. figure 5?15 shows a waveform example for a clock output enable. clkena is synchronous to the falling edge of the clock output. stratix iv devices also have an additional metastability register that aids in asynchronous enable and disable of the gclk and rclk networks. you can optionally bypass this register in the quartus ii software. figure 5?14. clkena implementation notes to figure 5?14 : (1) the r1 and r2 bypass paths are not avai lable for the pll exte rnal clock outputs. (2) the select line is static ally controlled by a bit setti ng in the configuration file ( .sof or .pof ). clkena gclk/ rclk/ pll_<#>_clkout (1) o u tp u t of clock select m u x (2) r1 r2 (1) (1) d q d q figure 5?15. clkena signals (1) note to figure 5?15 : (1) you can use the clkena signals to enable or disable th e gclk and rclk networks or the pll_ <#> _clkout pins. o u tp u t of clock select m u x clkena o u tp u t of a n d gate w ith r2 b ypassed o u tp u t of a n d gate w ith r2 not b ypassed 5?18 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 the pll can remain locked independent of the clkena signals because the loop-related counters are not affected. this feature is useful for applications that require a low-power or sleep mode. the clkena signal can also disable clock outputs if the system is not tolerant of frequenc y over-shoot during resynchronization. clock source control for plls the clock input to stratix iv plls comes from clock input multiplexers. the clock multiplexer inputs come from dedicated clock input pins, plls through the gclk and rclk networks, or from dedicated connections between adjacent top/bottom and left/right plls. the clock input sources to top/bottom and left/right plls (l2, l3, t1, t2, b1, b2, r2, and r3) are shown in figure 5?16 ; the corresponding clock input sources to left and right plls (l1, l4, r1, and r4) are shown in figure 5?17 . the multiplexer select lines are only set in the configuration file ( .sof or .pof ). after programmed, this block cannot be changed without loading a new configuration file ( .sof or .pof ). the quartus ii software automaticall y sets the multiplexer select signals depending on the clock sources selected in the design. figure 5?16. clock input multiplexer logic for l2, l3, t1, t2, b1, b2, r2, and r3 plls notes to figure 5?16 : (1) when the device is operati ng in user mode, input clock multiplexing is controlled through a configuration file ( .sof or .pof ) only and cannot be dynamically controlled. (2) n=0 for l2 and l3 plls; n=4 for b1 and b2 plls; n=8 for r2 and r3 plls, and n=12 for t1 and t2 plls. (3) you can drive the gclk or rclk input using an output from another pll, a pin-driven gclk or rclk, or through a clock control block provided the clock control block is fed by an output from another pll or a pin-driven dedicated gclk or rclk. an internally generated global si gnal or general purpose i/o pin cannot drive the pll. figure 5?17. clock input multiplexer logic for l1, l4, r1, and r4 plls notes to figure 5?17 : (1) dedicated clock input pins to the plls are l1, l4, r1, and r4, respectively. for example, pll_l1_clk is the dedicated clock input for pll_l1 . (2) you can drive the gclk or rclk input using an output from another pll, a pin-driven gclk or rclk, or through a clock control block provided the clock control block is fed by an output from another pll or a pin-driven dedicated gclk or rclk. an internally generated global si gnal or general purpose i/o pin cannot drive the pll. (3) the center clock pins can feed the corner plls on the same side directly through a de dicated path. however, these paths may not be fully compensated. 4 4 (1) (1) inclk0 inclk1 to the clock switchover bloc k clk[n+3..n] (2) gclk / rclk input (3) adjacent pll output inclk0 inclk1 clk[0..3] or clk[8..11] (3) gclk/rclk (2) pll_ chapter 5: clock networks and plls in stratix iv devices 5?19 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 cascading plls you can cascade the left/right and top/bottom plls through the gclk and rclk networks. in addition, where two left/right or top/bottom plls exist next to each other, there is a direct connection between them that does not require the gclk or rclk network. using this path reduces clock jitter when cascading plls. 1 stratix iv gx devices allow cascading the left and right plls to transceiver plls (cmu plls and receiver cdrs). f for more information, refer to the ?fpga fabric plls -transceiver plls cascading? section in the transceiver clocking in stratix iv devices chapter. when cascading plls in stratix iv devices, the source (upstream) pll must have a low-bandwidth setting while the destin ation (downstream) pll must have a high-bandwidth setting. ensure that there is no overlap of the bandwidth ranges of the two plls. f for more information about pll cascading in external memory interfaces designs, refer to the external memory phy interface (alt memphy) (nonafi) megafunction user guide . plls in stratix iv devices stratix iv devices offer up to 12 plls th at provide robust clock management and synthesis for device clock management, external system clock management, and high-speed i/o interfaces. the nomenclature for the plls follows their geographical location in the device floor plan. the plls that reside on the top and bottom sides of the device are named pll_t1 , pll_t2 , pll_b1 and pll_b2 ; the plls that reside on the left and right sides of the device are named pll_l1 , pll_l2 , pll_l3 , pll_l4 , pll_r1 , pll_r2 , pll_r3 , and pll_r4 . table 5?7 lists the number of plls availabl e in the stratix iv device family. table 5?7. pll availability for stratix iv devices (part 1 of 2) device package l1 l2 l3 l4 t1 t2 b1 b2 r1 r2 r3 r4 ep4s40g2 f1517 ? yy ? yyyy ? yy ? ep4s40g5 h1517 ? yy ? yyyy ? yy ? ep4s100g2 f1517 ? yy ? yyyy ? yy ? ep4s100g3 f1932 yyyyyyyyyyyy ep4s100g4 f1932 yyyyyyyyyyyy ep4s100g5 h1517 ? yy ? yyyy ? yy ? f1932 yyyyyyyyyyyy ep4se230 f780 ? y ?? y ? y ?? y ?? ep4se360 h780 ? y ?? y ? y ?? y ?? f1152 ? yy ? yyyy ? yy ? 5?20 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 all stratix iv plls have the same core analog structure with only minor differences in the features that are supported. table 5?8 lists the features of top/bottom and left/right plls in stratix iv devices. ep4se530 h1152 ? yy ? yyyy ? yy ? h1517 yyyyyyyyyyyy f1760 yyyyyyyyyyyy ep4se820 h1152 ? yy ? yyyy ? yy ? h1517 yyyyyyyyyyyy f1760 yyyyyyyyyyyy ep4sgx70 f780 ? y ?? y ? y ????? f1152 ? y ?? y ? y ?? y ?? ep4sgx110 f780 ? y ?? y ? y ????? f1152 ? y ?? y ? y ?? y ?? ep4sgx180 f780 ? y ?? y ? y ????? f1152 ? y ?? yyyy ? y ?? f1517 ? yy ? yyyy ? yy ? ep4sgx230 f780 ? y ?? y ? y ????? f1152 ? y ?? yyyy ? y ?? f1517 ? yy ? yyyy ? yy ? ep4sgx290 h780???? yyyy ???? f1152 ? y ?? yyyy ? y ?? f1517 ? yy ? yyyy ? yy ? f1760 yyyyyyyyyyyy f1932 yyyyyyyyyyyy ep4sgx360 h780???? yyyy ???? f1152 ? y ?? yyyy ? y ?? f1517 ? yy ? yyyy ? yy ? f1760 yyyyyyyyyyyy f1932 yyyyyyyyyyyy ep4sgx530 h1152 ? y ?? yyyy ? y ?? h1517 ? yy ? yyyy ? yy ? f1760 yyyyyyyyyyyy f1932 yyyyyyyyyyyy table 5?7. pll availability for stratix iv devices (part 2 of 2) device package l1 l2 l3 l4 t1 t2 b1 b2 r1 r2 r3 r4 table 5?8. pll features in stratix iv devices (part 1 of 2) (1) feature stratix iv top/bottom plls stratix iv left/right plls c (output) counters 10 7 m , n , c counter sizes 1 to 512 1 to 512 dedicated clock outputs 6 single-ended or 4 single-ended and 1 differential pair 2 single-ended or 1 differential pair chapter 5: clock networks and plls in stratix iv devices 5?21 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 clock input pins (2) 4 single-ended or 4 differential pin pairs 4 single-ended or 4 differential pin pairs external feedback input pin single-ended or differential single-ended only spread-spectrum input clock tracking yes (3) yes (3) pll cascading through gclk and rclk and a dedicated path between adjacent plls through gclk and rclk and dedicated path between adjacent plls (4) compensation modes all except lvds clock network compensation all except external feedback mode when using differential i/os pll drives lvdsclk and loaden no yes vco output drives the dpa clock no yes phase shift resolution down to 96.125 ps (5) down to 96.125 ps (5) programmable duty cycle yes yes output counter cascading yes yes input clock switchover yes yes notes to table 5?8 : (1) while there is pin compatib ility, there is no hard ip block placement compatibility. (2) general purpose i/o pins canno t drive the pll clock input pins. (3) provided input clock jitter is within input jitter tolera nce specifications. (4) the dedicated path between adjacent plls is not availabl e on l1, l4, r1, and r4 plls. (5) the smallest phase shift is determined by the voltage-controlled o scillator (vco) period divided by eight. for degree increm ents, the stratix iv device can shift all output frequenc ies in increments of at least 45 . smaller degree increments are possi ble depending on the frequency and divide parameters. table 5?8. pll features in stratix iv devices (part 2 of 2) (1) feature stratix iv top/bottom plls stratix iv left/right plls 5?22 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 figure 5?18 shows the location of plls in stratix iv devices. figure 5?18. pll locations in stratix iv devices pll_r1_clk pll-r4_clk clk[ 8 ..11] pll_l4_clk clk[0..3] l1 l2 l3 l4 r1 r2 r3 r4 t2 b1 b2 clk[4..7] clk[12..15] t1 q1 q4 q2 q3 left/right plls left/right plls left/right plls left/right plls top/bottom plls pll_l1_clk top/bottom plls top/bottom plls top/bottom plls chapter 5: clock networks and plls in stratix iv devices 5?23 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 stratix iv pll hardware overview stratix iv devices contain up to 12 plls with advanced clock management features. the goal of a pll is to synchronize the phas e and frequency of an internal or external clock to an input reference clock. there ar e a number of components that comprise a pll to achieve this phase alignment. stratix iv plls align the rising edge of th e input reference clock to a feedback clock using the phase-frequency detector (pfd). the falling edges are determined by the duty-cycle specifications. the pfd produces an up or down signal that determines whether the vco must operate at a higher or lower frequency. the output of the pfd feeds the charge pump and loop filter, which produces a control voltage for setting the vco frequency. if the pfd produces an up signal, the vco frequency increases. a down signal decreases the vco frequency. the pfd outputs these up and down signals to a charge pump. if the charge pump receives an up signal, current is driven into the loop filter. conversely, if the charge pump receives a down signal, current is drawn from the loop filter. the loop filter converts these up and down si gnals to a voltage that is used to bias the vco. the loop filter also removes glitches from the charge pump and prevents voltage over-shoot, which filters the jitter on the vco. the voltage from the loop filter determines how fast the vco operates. a divide counter ( m ) is inserted in the feedback loop to increase the vco frequency above the input reference frequency. vco frequency (f vco ) is equal to ( m ) times the input reference clock (f ref ). the input reference clock (f ref ) to the pfd is equal to the input clock (f in ) divided by the pre-scale counter ( n ). therefore, the feedback clock (f fb ) applied to one input of the pfd is locked to the f ref that is applied to the other input of the pfd. the vco output from the left and right p lls can feed seven po st-scale counters ( c[0..6] ), while the corresponding vco output from the top and bottom plls can feed ten post-scale counters ( c[0..9] ). these post-scale counters allow a number of harmonically related frequencies to be produced by the pll. 5?24 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 figure 5?19 shows a simplified block diagram of the major components of the stratix iv pll. 1 you can drive the gclk or rclk inputs using an output from another pll, a pin-driven gclk or rclk, or through a clock control block provided the clock control block is fed by an output from an other pll or a pin-driven dedicated gclk or rclk. an internally generated global signal or general purpose i/o pin cannot drive the pll. pll clock i/o pins each top and bottom pll supports six cloc k i/o pins, organized as three pairs of pins: 1st pair?two single-ended i/o or one differential i/o 2nd pair?two single-ended i/o or one differential external feedback input (fbp/fbn) 3rd pair?two single-ended i/ o or one differential input figure 5?19. stratix iv pll block diagram notes to figure 5?19 : (1) the number of post-scale counte rs is seven for left and right plls and ten for top and bottom plls. (2) this is the vco post-scale counter k . (3) the fbout port is fed by the m counter in stratix iv plls. clock switchover block inclk0 inclk1 dedicated clock inputs cascade input from adjacent pll pfdena clkswitch clkbad0 clkbad1 activeclock pfd lock circuit locked n cp lf vco 2 (2) gclk/rclk 8 4 fbin diffioclk network gclk/rclk network no compensation mode zdb, external feedback modes lvds compensation mode source synchronous, normal modes c0 c1 c2 c3 cn m (1) pll output mux casade output to adjacent pll gclks rclks external clock outputs diffioclk from left/right plls load_en from left/right plls fbout (3) external memory interface dll 8 8 to dpa block on left/right plls /2, /4 chapter 5: clock networks and plls in stratix iv devices 5?25 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 figure 5?20 shows the clock i/o pins associat ed with the top and bottom plls. figure 5?20. external clock outputs for top and bottom plls notes to figure 5?20 : (1) you can feed these clock output pins using any one of the c[9..0] , m counters . (2) the clkout0p and clkout0n pins can be either single-ended or differential clock outputs. the clkout1 and clkout2 pins are dual-purpose i/o pins that you can use as two single-ended outputs or one differe ntial external feedback input pin. the clkout3 and clkout4 pins are two single-ended output pins. (3) these external clock enab le signals are available only when using the altclkct rl megafunction. top/bottom plls c2 c3 c4 c6 c7 c5 pll_<#>_clkout3 (1), (2) c 8 c0 c1 c9 internal logic pll_<#>_clkout4 (1), (2) pll_<#>_fbn/clkout2 (1), (2) pll_<#>_fbp/clkout1 (1), (2) pll_<#>_clkout0n (1), (2) pll_<#>_clkout0p (1), (2) clkena0 (3) clkena1 (3) clkena3 (3) clkena2 (3) clkena4 (3) clkena5 (3) m(f b o u t) 5?26 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 any of the output counters ( c[9..0] on the top and bottom plls and c[6..0] on the left and right plls) or the m counter can feed the dedicated external clock outputs, as shown in figure 5?20 and figure 5?21 . therefore, one counter or frequency can drive all output pins availa ble from a given pll. each left and right pll supports two clock i/o pins, configured as either two single-ended i/os or one differential i/o pair. when using both pins as single-ended i/os, one of them can be the clock output wh ile the other pin is the external feedback input (fb) pin. therefore, for single-ended i/o standards, the left and right plls only support external feedback mode. each pin of a single-ended output pair can either be in-phase or 180 out-of-phase. the quartus ii software places the not gate in the design into the ioe to implement the 180 phase with respect to the other pi n in the pair. the clock output pin pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, differen tial high-speed transceiver logic (hstl), and differential sstl. f to determine which i/o standards are suppo rted by the pll clock input and output pins, refer to the i/o features in stratix iv devices chapter. stratix iv plls can also drive out to any regular i/o pin through the gclk or rclk network. you can also use the external clock output pins as user i/o pins if you do not need external pll clocking. figure 5?21. external clock outputs for left and right plls notes to figure 5?21 : (1) you can feed these clock output pins using any one of the c[6..0], m counters. (2) the clkout0p and clkout0n pins are dual-purpose i/o pins that you can use as tw o single-ended outputs or one single-ended output and one external feedback input pin. (3) these external clock enab le signals are available only when using the altclkct rl megafunction. left/right plls c2 c3 c4 c6 c5 clke n a0 (3) c0 c1 internal logic pll_ chapter 5: clock networks and plls in stratix iv devices 5?27 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 pll control signals you can use the pfdena , areset , and locked signals to observe and control pll operation and resynchronization. pfdena use the pfdena signal to maintain the most recent locked frequency so your system has time to store its current settings before shutting down. the pfdena signal controls the pfd output with a programmable gate. if you disable pfd, the vco operates at its most recent set value of control voltage and frequency, with some long-term drift to a lower frequency. the pll continues running even if it goes out-of-lock or the input clock is disabled. you can use either your own control signal or the control signals available from the clock switchover circuit ( activeclock , clkbad[0] , or clkbad[1] ) to control pfdena . areset the areset signal is the reset or resynchroni zation input for each pll. the device input pins or internal logic can drive these input signals. when areset is driven high, the pll counters reset, clearing the pll output and placing the pll out-of-lock. the vco is then set back to its nominal setting. when areset is driven low again, the pll resynchronizes to its input as it re-locks. you must assert the areset signal every time the pll loses lock to guarantee the correct phase relationship between the pll input and output clocks. you can set up the pll to automatically reset (self reset) after a loss-of-lock condition using the quartus ii megawizard ? plug-in manager. you must include the areset signal in designs if either of the following conditions is true: pll reconfiguration or clock switchover is enabled in the design phase relationships between the pll input and output clocks must be maintained after a loss-of-lock condition 1 if the input clock to the pll is not toggling or is unstable after power up, assert the areset signal after the input clock is stable and within specifications. locked the locked signal output of the pll indicates that the pll has locked onto the reference clock and the pll clock outputs are operating at the desired phase and frequency set in the quartus ii megawizard plug-in manager. the lock detection circuit provides a signal to the core logic that gives an indication when the feedback clock has locked onto the reference clock both in phase and frequency. 1 altera recommends using the areset and locked signals in your designs to control and observe the status of your pll. 5?28 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 clock feedback modes stratix iv plls support up to six different clock feedback modes. each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. table 5?9 lists the clock feedback modes supported by the stratix iv device plls. 1 the input and output delays are fully compensated by a pll only when using the dedicated clock input pins associated wi th a given pll as the clock source. for example, when using pll_t1 in normal mode, the clock delays from the input pin to the pll clock output-to-destination regist er are fully compensated, provided the clock input pin is one of the following two pins: clk14 and clk15 . compensated pins are only in the same i/o bank as the pll. when an rclk or gclk network drives the pll, the input and output delays may not be fully compensated in the quartus ii software. another example is when you configure pll_t2 in zero-delay buffer mode and the pll input is driven by a dedicated clock input pin, a fully compensated clock path results in zero-delay between the cloc k input and one of the output clocks from the pll. if the pll input is instead fed by a non-dedicated input (using the gclk network), the output clock may not be perfectly aligned with the input clock. table 5?9. clock feedback mode availability clock feedback mode availability top and bottom plls left and right plls source-synchronous yes yes no-compensation yes yes normal yes yes zero-delay buffer (zdb) yes yes external feedback (1) yes yes (2) lvds compensation no yes notes to table 5?9 : (1) the high-bandwidth pll setting is not supported in external feedback mode. (2) external feedback mode is supporte d for single-ended inputs and outpu ts only on the left and right plls. chapter 5: clock networks and plls in stratix iv devices 5?29 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 source synchronous mode if data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any ioe input register. figure 5?22 shows an example waveform of the clock and data in this mode. altera recommends source synchronous mode for so urce-synchronous data transfers. data and clock signals at the ioe experience simi lar buffer delays as long as you use the same i/o standard. source-synchronous mode compensates for the delay of the clock network used plus any difference in the delay between these two paths: data pin to the ioe register input clock input pin to the pll pfd input the stratix iv pll can compensa te multiple pad-to-input-register paths, such as a data bus when it is set to use source-s ynchronous compensation mode. you can use the ?pll compensation? assignment in the qu artus ii software assignment editor to select which input pins are used as the pll compensation targets. you can include your entire data bus, provided the input re gisters are clocked by the same output of a source-synchronous-compensated pll. in order for the clock delay to be properly compensated, all of the input pins must be on the same side of the device. the pll compensates for the input pin with the long est pad-to-register delay among all input pins in the compensated bus. if you do not make the ?pll compensati on? assignment, the quartus ii software automatically selects all of the pins driven by the compensated output of the pll as the compensation target. figure 5?22. phase relationship between clock and data in source-synchronous mode data pin pll reference clock at input pin data at register clock at register 5?30 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 source-synchronous mode for lvds compensation the goal of source-synchronous mode is to maintain the same data and clock timing relationship seen at the pins of the intern al serializer/deseriali zer (serdes) capture register, except that the clock is inverted (180 phase shift). thus, source-synchronous mode ideally compensates for the delay of the lvds clock network plus any difference in delay between these two paths: data pin-to-serdes capture register clock input pin-to-serdes capture register. in addition, the output counter must provide the 180 phase shift figure 5?23 shows an example waveform of the clock and data in lvds mode. no-compensation mode in no-compensation mode, the pll does not compensate for any clock networks. this mode provides better jitter performance because the clock feedback into the pfd passes through less circuitry. both the p ll internal- and external-clock outputs are phase-shifted with respect to the pll clock input. figure 5?24 shows an example waveform of the pll clocks? phase relationship in no-compensation mode. figure 5?23. phase relationship between the clock and data in lvds mode figure 5?24. phase relationship between the pll clocks in no compensation mode note to figure 5?24 : (1) the pll clock outputs lag the pll i nput clocks depending on routine delays. data pin pll reference clock at input pin data at register clock at register pll reference clock at the input pin pll clock at the register clock port (1) external pll clock outputs (1) phase aligned chapter 5: clock networks and plls in stratix iv devices 5?31 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 normal mode an internal clock in normal mode is phase-aligned to the input clock pin. the external clock-output pin has a phase delay relative to the clock input pin if connected in this mode. the quartus ii software timing analyz er reports any phase difference between the two. in normal mode, the delay introduced by the gclk or rclk network is fully compensated. figure 5?25 shows an example waveform of the pll clocks? phase relationship in normal mode. zero-delay buffer (zdb) mode in zdb mode, the external clock output pin is phase-aligned with the clock input pin for zero-delay through the device. when using this mode, you must use the same i/o standard on the input clocks and output cl ocks to guarantee clock alignment at the input and output pins. zdb mode is supported on all stratix iv plls. when using stratix iv plls in zdb mode, along with single-ended i/o standards, to ensure phase alignment between the clk pin and the external clock output ( clkout ) pin, you must instantiate a bi-directional i/o pin in the design to serve as the feedback path connecting the fbout and fbin ports of the pll. the pll uses this bi-directional i/o pin to mimic, and compen sate for, the output delay from the clock output port of the pll to the external clock output pin. figure 5?26 shows zdb mode in stratix iv plls. when using zdb mode, you cannot use differential i/o standards on the pll clock input or output pins. 1 the bi-directional i/o pin that you instantiate in your design must always be assigned a single-ended i/o standard. figure 5?25. phase relationship between the pll clocks in normal mode note to figure 5?25 : (1) the external clock out put can lead or lag the pll internal clock signals. pll clock at the register clock port dedicated pll clock outputs (1) phase aligned pll reference clock at the input pin 5?32 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 1 when using zdb mode, to avoi d signal reflection, do not place board traces on the bi-directional i/o pin. figure 5?27 shows an example waveform of the pll clocks? phase relationship in zdb mode. external feedback mode in external feedback mode, the external feedback input pin ( fbin ) is phase-aligned with the clock input pin, as shown in figure 5?28 . aligning these clocks allows you to remove clock delay and skew between devices. this mode is supported on all stratix iv plls. in external feedback mode, the output of the m counter ( fbout ) feeds back to the pll fbin input (using a trace on the board) becomi ng part of the feed back loop. also, use one of the dual-purpose external clock outputs as the fbin input pin in this mode. when using external feedback mode, you must use the same i/o standard on the input clock, feedback input, and output clocks. left and right plls support this mode when using single-ended i/o standards only. figure 5?26. zdb mode in stratix iv plls note to figure 5?26 : (1) the bidirectional i/o pin must be assigned to the pll_< #> _fb_clkout0p pin for left and right plls and to the pll_< #> _fbp_/clkout1 pin for top and bottom plls. inclk fbin fbout pll_<#>_clkout# n pfd cp/lf vco c0 c1 m bidirectional i/o pin (1) pll_<#>_clkout# figure 5?27. phase relationship between the pll clocks in zdb mode note to figure 5?27 : (1) the internal pll clock ou tput can lead or lag the external pll clock outputs. pll clock at the register clock port (1) dedicated pll clock o u tp u ts phase aligned pll reference clock at the inp u t pin chapter 5: clock networks and plls in stratix iv devices 5?33 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 figure 5?28 shows an example waveform of the phase relationship between the pll clocks in external feedback mode. figure 5?29 shows external feedback mode impl ementation in stratix iv devices. clock multiplication and division each stratix iv pll provides clock sy nthesis for pll output ports using m /( n * post-scale counter) scaling factors. th e input clock is divided by a pre-scale factor, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a un ique post-scale counter that divides down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. for ex ample, if the output frequencies required from one pll are 33 and 66 mhz, the quartus ii software sets the vco to 660 mhz (the least common multiple of 33 and 66 mhz within the vco range). then the post-scale counters scale down the vco frequency for each output port. figure 5?28. phase relationship between the pll clocks in external feedback mode note to figure 5?28 : (1) the pll clock outputs can lead or lag the fbin clock input. dedicated pll clock o u tp u ts (1) pll clock at the register clock port ( 1) f b in clock inp u t pin phase aligned pll reference clock at the inp u t pin figure 5?29. external feedback mode in stratix iv devices inclk fbin fbout external board trace pll_<#>_clkout# pll_<#>_clkout# n pfd cp/lf vco c0 c1 m 5?34 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 each pll has one pre-scale counter, n , and one multiply counter, m , with a range of 1 to 512 for both m and n . the n counter does not use duty-cycle control because the only purpose of this counter is to calculat e frequency division. there are seven generic post-scale counters per left or right pll an d ten post-scale counters per top or bottom pll that can feed the gclks, rclks, or external clock outputs. these post-scale counters range from 1 to 512 with a 50% du ty cycle setting. the high- and low-count values for each counter range from 1 to 256. the sum of the high- and low-count values chosen for a design selects the divide value for a given counter. the quartus ii software automatically ch ooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the altpll megafunction. post-scale counter cascading stratix iv plls support post-scale counter cascading to create counters larger than 512. this is automatically implemented in the quartus ii software by feeding the output of one c counter into the input of the next c counter, as shown in figure 5?30 . when cascading post-scale counters to implement a larger division of the high-frequency vco clock, the cascaded co unters behave as one counter with the product of the individual counter settings. for example, if c0 = 40 and c1 = 20, the cascaded value is c0 c1 = 800. 1 post-scale counter cascading is set in the configuration file. you cannot set this using pll reconfiguration. figure 5?30. counter cascading note to figure 5?30 : (1) n = 6 or n = 9 c0 c1 c2 cn c3 c4 v co o u tp u t v co o u tp u t v co o u tp u t v co o u tp u t v co o u tp u t v co o u tp u t (1) from preceding post-scale co u nter chapter 5: clock networks and plls in stratix iv devices 5?35 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 programmable duty cycle the programmable duty cycle allows plls to generate clock outputs with a variable duty cycle. this feature is supported on the pll post-scale counters. the duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. to determine duty cycle choices, the quartus i i software uses the frequency input and the required multiply or divide rate. th e post-scale counter value determines the precision of the duty cycle. precision is defined as 50% divided by the post-scale counter value. for example, if the c0 counter is 10, steps of 5% are possible for duty-cycle choices from 5% to 90%. if the pll is in external feedback mode, se t the duty cycle for the counter driving the fbin pin to 50%. combining the programmabl e duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. programmable phase shift use phase shift to implement a robust solution for clock delays in stratix iv devices. implement phase shift by using a combination of the vco phase output and the counter starting time. a comb ination of vco phase output and counter starting time is the most accurate method of inserting de lays because it is only based on counter settings, which are independent of process, voltage, and temperature (pvt). you can phase-shift the output clocks from th e stratix iv plls in either of these two resolutions: fine resolution using vco phase taps coarse resolution using counter starting time implement fine-resolution phase shifts by allowing any of the output counters ( c[n..0]) or the m counter to use any of the eight phases of the vco as the reference clock. this allows you to adjust the delay time with a fine resolution. equation 5?1 shows the minimum delay time that you can insert using this method. where f ref is the input reference clock frequency. for example, if f ref is 100 mhz, n is 1, and m is 8, then f vco is 800 mhz and fine equals 156.25 ps. this phase shift is defined by the pll operating frequency, which is governed by the reference clock frequency and the counter settings. equation 5?1. fine-resolution phase shift fine = t vco = = 1 8 1 8 f vco n 8 mf ref ? 5?36 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 equation 5?2 shows the coarse-resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks. where c is the count value set for the counter delay time (this is the initial setting in the ?pll usage? section of the compilation re port in the quartus ii software). if the initial value is 1, c ? 1 = 0 phase shift. figure 5?31 shows an example of phase-shift insertion with fine resolution using the vco phase-taps method. the eight phases from the vco are shown and labeled for reference. for this example, clk0 is based on the 0phase from the vco and has the c value for the counter set to one. the clk1 signal is divided by four, two vco clocks for high time and two vco clocks for low time. clk1 is based on the 135 phase tap from the vco and also has the c value for the counter set to one. in this case, the two clocks are offset by 3 fine . clk2 is based on the 0phase from the vco but has the c value for the counter set to three . this arrangement creates a delay of 2 coarse (two complete vco periods). you can use coarse- and fine-phase shifts to implement clock delays in stratix iv devices. stratix iv devices support dynamic phase-shifting of vco phase taps only. you can reconfigure the phase shift any number of times. each phase shift takes about one scanclk cycle, allowing you to implem ent large phase shifts quickly. equation 5?2. coarse-resolution phase shift coarse = = c ? 1 f (c ? 1) n mf ref v co ? ? figure 5?31. delay insertion using vco phase output and counter delay time t d0-1 t d0-2 1/8 t vco t vco 0 90 135 180 225 270 315 clk0 clk1 clk2 45 chapter 5: clock networks and plls in stratix iv devices 5?37 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 programmable bandwidth stratix iv plls provide advanced control of the pll bandwidth using the pll loop?s programmable characteristics, including loop filter and charge pump. background pll bandwidth is the measure of the pll?s ability to track the input clock and its associated jitter. the closed-loop gain 3 db frequency in the pll determines pll bandwidth. bandwidth is approximately th e unity gain point for open loop pll response. as figure 5?32 shows, these points correspond to approximately the same frequency. stratix iv plls provide three ba ndwidth settings?low, medium (default), and high. figure 5?32. open- and closed-loop response bode plots increasing the pll's bandwidth in effect pushes the open loop response out. gain gain 0 db frequency frequency open-loop reponse bode plot closed-loop reponse bode plot 5?38 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 a high-bandwidth pll provides a fast lock time and tracks jitter on the reference clock source, passing it through to the p ll output. a low-bandwidth pll filters out reference clock jitter but increases lock time . stratix iv plls allow you to control the bandwidth over a finite range to customiz e the pll characteristics for a particular application. the programmable bandwidth feature in stratix iv plls benefits applications requiring clock switchover. a high-bandwidth pll can benefit a system that must accept a spread-spectrum clock signal. stratix iv plls can track a spread-spectrum clock by using a high-bandwidth setting. using a low-bandwidth setting in this case could cause the pll to filter out the jitter on the input clock. a low-bandwidth pll can benefit a system using clock switchover. when clock switchover occurs, the pll input temporar ily stops. a low-bandwidth pll reacts more slowly to changes on its input clock and takes longer to drift to a lower frequency (caused by input stopping) than a high-bandwidth pll. implementation traditionally, external components such as the vco or loop filter control a pll?s bandwidth. most loop filters consist of passive components such as resistors and capacitors that take up unnecessary boar d space and increase cost. with stratix iv plls, all the components are contained within the device to increase performance and decrease cost. when you specify the bandwidth setting (low, medium, or high) in the altpll megawizard ? plug-in manager, the quartus ii so ftware automatically sets the corresponding charge pump and loop filter ( icp , r , c ) values to achieve the desired bandwidth range. figure 5?33 shows the loop filter and compon ents that you can set using the quartus ii software. the components are the loop filter resistor, r, the high frequency capacitor, c h , and the charge pump current, i up or i dn . figure 5?33. loop filter programmable components i up i d n c h pfd r c chapter 5: clock networks and plls in stratix iv devices 5?39 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 spread-spectrum tracking stratix iv devices can accept a spread-s pectrum input with typical modulation frequencies. however, the device cannot au tomatically detect that the input is a spread-spectrum signal. instead, the input sign al looks like deterministic jitter at the input of the pll. stratix iv plls can track a spread-spectrum input clock as long as it is within input-jitter tolerance specifications. stratix iv devices cannot internally generate spread-spectrum clocks. clock switchover the clock switchover feature allows the pl l to switch between two reference input clocks. use this feature for clock redundancy or for a dual-clock domain application such as in a system that turns on the re dundant clock if the previous clock stops running. the design can perform clock switch over automatically when the clock is no longer toggling or based on a user control signal, clkswitch . the following clock switchover mode s are supported in stratix iv plls: automatic switchover?the clock sense ci rcuit monitors the current reference clock and if it stops toggling, automatically switches to the other inclk0 or inclk1 clock. manual clock switchover?clock switchover is controlled using the clkswitch signal. when the clkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles, the re ference clock to the pll is switched from inclk0 to inclk1 , or vice-versa. automatic switchover with manual ov erride?this mode combines automatic switchover and manual clock switchover. when the clkswitch signal goes high, it overrides the automatic clock switchover function. as long as the clkswitch signal is high, further switchover action is blocked. 5?40 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 stratix iv plls support a fully configurable clock switchover capability. figure 5?34 shows a block diagram of the automatic swit chover circuit built into the pll. when the current reference clock is not present, the clock sense block automatically switches to the backup clock for pll reference. th e clock switchover circuit also sends out three status signals? clkbad[0] , clkbad[1] , and activeclock ?from the pll to implement a custom switchover circuit in the logic array. you can select a clock source as the backup clock by connecting it to the inclk1 port of the pll in your design. automatic clock switchover use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the pll stops toggling. for example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal ( clksw ) that controls the multiplexer select input, as shown in figure 5?34 . in this case, inclk1 becomes the reference clock for the pll. when using automatic switchover mode, you can switch back and forth between inclk0 and inclk1 any number of times when one of the two clocks fails and the other clock is available. when using automatic clock switchover mode, the following requirements must be satisfied: both clock inputs must be running the period of the two clock inputs can differ by no more than 100% (2) if the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the clkbad[0..1] signals are not valid. also, if both clock inputs are not the same frequency, but their period difference is within 100%, the clock sense block detects when a clock stops toggling, but the pll may lose lock after the switchover is completed and needs time to re-lock. 1 altera recommends resetting the pll using the areset signal to maintain the phase relationships between the pll input and output clocks when using clock switchover. figure 5?34. automatic clock switchover circuit block diagram s w itcho v er state machine clock sense n co u nter pfd clks w itch acti v eclock clk b ad[1] clk b ad[0] m u xo u t inclk0 inclk1 r efclk fbclk clk s w clock s w itch control logic chapter 5: clock networks and plls in stratix iv devices 5?41 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 in automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. when they are asserted, the clock sense block has detected that the corresponding clock input has stopped toggling. these two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%. the activeclock signal indicates which of the two clock inputs ( inclk0 or inclk1 ) is being selected as the reference clock to the pll. when the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal. figure 5?35 shows an example waveform of the switchover feature when using automatic switchover mode. in this example, the inclk0 signal is stuck low. after the inclk0 signal is stuck at low for approximately two clock cycles, the clock sense circuitry drives the clkbad[0] signal high. also, because the reference clock signal is not toggling, the switchover state machine controls the multiplexer through the clkswitch signal to switch to the backup clock, inclk1 . manual override in automatic switchover with manual override mode, you can use the clkswitch input for user- or system-controlled switch conditions. you can use this mode for same-frequency switchover, or to switch be tween inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 200 mhz, you must control switchover using clkswitch because the automatic clock-sens e circuitry cannot monitor clock input ( inclk0 and inclk1 ) frequencies with a frequency difference of more than 100% (2). this feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation. you must choose the backup clock frequency and set the m , n , c , and k counters accordingly so the vco operates within the recommended operating frequency range of 600 to 1,600 mhz. the altpll megawizard plug-in manager notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement. figure 5?35. automatic switchover af ter loss of clock detection note to figure 5?35 : (1) switchover is enabled on the falling edge of inclk0 or inclk1 , depending on which clock is available. in this figure, switchover is enabled on the falling edge of inclk1 . inclk0 inclk1 muxout clkbad0 clkbad1 (1) activeclock 5?42 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 figure 5?36 shows a clock switchover waveform controlled by clkswitch . in this case, both clock sources are functional and inclk0 is selected as the reference clock; clkswitch goes high, which starts the switchover sequence. on the falling edge of inclk0 , the counter?s reference clock, muxout , is gated off to prevent clock glitching. on the falling edge of inclk1 , the reference clock multiplexer switches from inclk0 to inclk1 as the pll reference and the activeclock signal changes to indicate which clock is currently feeding the pll. in automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch signal. as both clocks are still fu nctional during the manual switch, neither clkbad signal goes high. because the sw itchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0 . when the clkswitch signal goes high again, the process repeats. clkswitch and automatic switch only work if the clock being switched to is available. if the clock is not available, the state machine waits until the clock is available. figure 5?36. clock switchover using the clkswitch (manual) control (1) note to figure 5?36 : (1) to initiate a manual cloc k switchover event, both inclk0 and inclk1 must be running when the clkswitch signal goes high. inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 chapter 5: clock networks and plls in stratix iv devices 5?43 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 manual clock switchover in manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the pll. by default, inclk0 is selected. a low-to-high transition on clkswitch and clkswitch being held high for at least three inclk cycles initiates a clock switchover event. you must bring clkswitch back low again in order to perform another switchover event in the future. if you do not require another switchover event in the future, you can leave clkswitch in a logic high state after the initial switch. pulsing clkswitch high for at least three inclk cycles performs another switchover event. if inclk0 and inclk1 are different frequencies and are always running, the clkswitch minimum high time must be greater than or equal to three of the slower frequency inclk0 or inclk1 cycles. figure 5?37 shows a block diagram of the manual switchover circuit. f for more information about pll software support in the quartus ii software, refer to the phase-locked loop (altpll) megafunction user guide . guidelines when implementing clock switchover in stratix iv plls, use the following guidelines: automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 100% (2) of each other. failin g to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function properly. when using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2). however, differences in frequency, phase, or both, of the two clock sources will likely cause the pll to lose lock. resetting the pll ensures that the correct phase relationships are maintained between the input and output clocks. 1 both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual clock switchover event. failing to meet this requirement causes the clock switchover to not function properly. applications that require a clock switch over feature and a small frequency drift must use a low-bandwidth pll. the low-bandwidth pll reacts more slowly than a high-bandwidth pll to reference input clock changes. when switchover happens, a low-bandwidth pll propagates the stopping of the clock to the output more slowly than a high-bandwidth pll. however, be aware that the low-bandwidth pll also increases lock time. figure 5?37. manual clock switchover circuitry in stratix iv plls n co u nter pfd f b cl k clks w itch inclk0 inclk1 m u xo u t r efclk clock s w itch control logic 5?44 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 after a switchover occurs, there may be a finite resynchronization period for the pll to lock onto a new clock. the exact amount of time it takes for the pll to re-lock depends on the pll configuration. the phase relationship between the input clock to the pll and the output clock from the pll is important in your design. assert areset for at least 10 ns after performing a clock switchover. wait for the locked signal to go high and be stable before re-enabling the output clocks from the pll. figure 5?38 shows how the vco frequency gradually decreases when the current clock is lost and then increases as the vco locks on to the backup clock. disable the system during clock switchover if it is not tolerant of frequency variations during the pll resynchr onization period. you can use the clkbad[0] and clkbad[1] status signals to turn off the pfd ( pfdena = 0 ) so the vco maintains its most recent frequency. you can also use the state machine to switch over to the secondary clock. when the pfd is re-enabled, output clock-enable signals ( clkena ) can disable clock outputs during the switchover and resynchronization period. when the lock indication is stable, the system can re-enable the output clocks. pll reconfiguration plls use several divide counters and different vco phase taps to perform frequency synthesis and phase shifts. in stratix iv plls, you can reconfigure both the counter settings and phase-shift the pll output cloc k in real time. you can also change the charge pump and loop-filter components, which dynamically affects pll bandwidth. you can use these pll components to update the output-clock frequency and pll bandwidth and to phase-shift in real time, without reconfiguring the entire stratix iv device. the ability to reconfigure the pll in real time is useful in applications that operate at multiple frequencies. it is also useful in prototyping environments, allowing you to sweep pll output frequencies and adjust the output-clock phase dynamically. for instance, a system generating test patterns is required to generate and transmit patterns at 75 or 150 mhz, depending on th e requirements of the device under test. reconfiguring the pll components in real time allows you to switch between two such output frequencies within a few microseconds. you can also use this feature to adjust clock-to-out ( tco ) delays in real time by changing the pll output clock phase shift. this approach eliminates the need to regenerate a configuration file with the new pll settings. figure 5?38. vco switchover operating frequency f vco primary clock stops running switchover occurs vco tracks secondary clock chapter 5: clock networks and plls in stratix iv devices 5?45 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 pll reconfiguration ha rdware implementation the following pll components are reconfigurable in real time: pre-scale counter ( n ) feedback counter ( m ) post-scale output counters ( c0 - c9 ) post vco divider ( k ) dynamically adjust the charge-pump current ( icp ) and loop-filter components ( r , c ) to facilitate reconfiguration of the pll bandwidth figure 5?39 shows how you can dynamically adju st the pll counter settings by shifting their new settings into a serial shift- register chain or scan chain. serial data is input to the scan chain using the scandata port. shift registers are clocked by scanclk . the maximum scanclk frequency is 100 mhz. serial data is shifted through the scan chain as long as the scanclkena signal stays asserted. after the last bit of data is clocked, asserting the configupdate signal for at least one scanclk clock cycle causes the pll configuration bits to be synchron ously updated with the data in the scan registers. 1 the counter settings are updated synchron ously to the clock frequency of the individual counters. therefore, all counters are not updated simultaneously. figure 5?39. pll reconfiguration scan chain (1) notes to figure 5?39 : (1) stratix iv left and right plls support c0 - c6 counters. (2) i = 6 or i = 9. (3) this figure shows the corres ponding scan register for the k counter in between the scan registers for the charge pump and loop filter. the k counter is physically located after the vco. /ci (2) /ci-1 /c2 /c1 /c0 /m /n scanclk scandone scandata lf/k/cp (3) configupdate inclk pfd vco scanclkena scandataout from m counter from n counter 5?46 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 table 5?10 lists how these signals can be driven by the pld logic array or i/o pins. to reconfigure the pll counters, follow these steps: 1. the scanclkena signal is asserted at least one scanclk cycle prior to shifting in the first bit of scandata ( d0 ). 2. serial data ( scandata ) is shifted into the scan chain on the second rising edge of scanclk . 3. after all 234 bits (top and bottom plls) or 180 bits (left and right plls) have been scanned into the scan chain, the scanclkena signal is de-asserted to prevent inadvertent shifting of bits in the scan chain. 4. the configupdate signal is asserted for one scanclk cycle to update the pll counters with the contents of the scan chain. 5. the scandone signal goes high, indicating the pll is being reconfigured. a falling edge indicates the pll counters have been updated with new settings. 6. reset the pll using the areset signal if you make any changes to the m , n , or post-scale output c counters or to the icp , r , or c settings. 7. you can repeat steps 1-5 to reconfigure the pll any number of times. table 5?10. real-time pll reconfiguration ports pll port name description source destination scandata serial input data stream to scan chain. logic array or i/o pin pll reconfiguration circuit scanclk serial clock input signal. this clock can be free running. gclk, rclk or i/o pins pll reconfiguration circuit scanclkena enables scanclk and allows the scandata to be loaded in the scan chain. active high. logic array or i/o pin pll reconfiguration circuit configupdate writes the data in the scan chain to the pll. active high. logic array or i/o pin pll reconfiguration circuit scandone indicates when the pll has finished reprogramming. a rising edge indicates the pll has begun reprogramming. a falling edge indicates the pll has finished reprogramming. pll reconfiguration circuit logic array or i/o pins scandataout used to output the contents of the scan chain. pll reconfiguration circuit logic array or i/o pins chapter 5: clock networks and plls in stratix iv devices 5?47 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 figure 5?40 shows a functional simulation of the pll reconfiguration feature. 1 when you reconfigure the counter clock frequency, you cannot reconfigure the corresponding counter phase shift settings using the same interface. instead, reconfigure the phase shifts in real time using the dynamic phase shift reconfiguration interface. if you reconfigure the counter frequency, but wish to keep the same non-zero phase shift setting (for exampl e, 90) on the clock output, you must reconfigure the phase shift immediately after reconfiguring the counter clock frequency. post-scale counters (c0 to c9) you can reconfigure the multiply or divide values and duty cycle of post-scale counters in real time. each counter has an 8-bit high-time setting and an 8-bit low-time setting. the duty cycle is the rati o of output high- or low-time to the total cycle time, which is the sum of the two. ad ditionally, these counters have two control bits, rbypass , for bypassing the counter, and rselodd , to select the output clock duty cycle. when the rbypass bit is set to 1, it bypasses the co unter, resulting in a divide by 1. when the rbypass bit is set to 0, the high- and low-time counters are added to compute the effective division of the vco output frequency. for example, if the post-scale divide factor is 10, the high- an d low-count values can be set to 5 and 5, respectively, to achieve a 50% - 50% duty cy cle. the pll implements this duty cycle by transitioning the output clock from high to low on the rising edge of the vco output clock. however, a 4 and 6 setting for the high- and low-count values, respectively, produces an output cl ock with a 40% - 60% duty cycle. figure 5?40. pll reconfiguration waveform scandata scanclk scanclkena scandataout configupdate scandone areset d0_old dn_old dn dn (msb) (lsb) d0 5?48 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 the rselodd bit indicates an odd divide factor for the vco output frequency along with a 50% duty cycle. for example, if the po st-scale divide factor is 3, the high- and low-time count values could be set to 2 and 1, respectively , to achieve this division. this implies a 67% - 33% duty cycle. if yo u need a 50% - 50% duty cycle, you can set the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor. the pll implements this duty cycle by tran sitioning the output clock from high to low on a falling edge of the vco output clock. when you set rselodd =1, you subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. for example: high-time count = 2 cycles low-time count = 1 cycle rselodd = 1 effectively equals: high-time count = 1.5 cycles low-time count = 1.5 cycles duty cycle = (1.5/3) % high-time co unt and (1.5/3) % low-time count scan chain description the length of the scan chain varies for di fferent stratix iv plls. the top and bottom plls have ten post-scale counters and a 23 4-bit scan chain, while the left and right plls have seven post-s cale counters and a 180-bit scan chain. table 5?11 lists the number of bits for each co mponent of a stratix iv pll. table 5?11. top and bottom pll reprogramming bits (part 1 of 2) block name number of bits total counter other (1) c9 (2) 16 2 18 c8 16 2 18 c7 16 2 18 c6 (3) 16 2 18 c5 16 2 18 c4 16 2 18 c3 16 2 18 c2 16 2 18 c1 16 2 18 c0 16 2 18 m16218 n16218 charge pump current 0 3 3 vco post-scale divider ( k )101 chapter 5: clock networks and plls in stratix iv devices 5?49 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 table 5?11 lists the scan chain order of pll co mponents for the top and bottom plls, which have 10 post-scale counters. the order of bits is the same for the left and right plls, but the reconfiguration bits st art with the c6 post-scale counter. figure 5?41 shows the scan-chain order of pll components for the top and bottom plls. figure 5?42 shows the scan-chain bit-order sequence for post-scale counters in all stratix iv plls. loop filter capacitor (4) 022 loop filter resistor 0 5 5 unused cp/lf 0 7 7 total number of bits ? ? 234 notes to table 5?11 : (1) includes two control bits, rbypass , for bypassing th e counter, and rselodd , to select the output clock duty cycle. (2) the lsb for the c9 low-c ount value is the first bit shifted into the scan chain for the top and bottom plls. (3) the lsb for the c6 low-c ount value is the first bit shifted into the scan chain for the left and right plls. (4) the msb for the loop filter is th e last bit shifted into the scan chain. table 5?11. top and bottom pll reprogramming bits (part 2 of 2) block name number of bits total counter other (1) figure 5?41. scan-chain order of pll components for top and bottom plls (1) note to figure 5?41 : (1) left and right plls have the same scan-chain order. the post-scale counters end at c6. datain msb lf k cp lsb n m c0 c1 c2 c3 c4 c5 c6 c7 c8 datao u t c9 figure 5?42. scan-chain bit-order sequence for post-scale counters in stratix iv plls datain rbypass hb 7 hb 6 hb 5 hb 4 hb 3 hb 2 hb 1 hb 0 rselodd lb 7 lb 6 lb 5 lb 4 lb 3 lb 2 lb 1 lb 0 datao u t 5?50 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 charge pump and loop filter you can reconfigure the charge-pump and loop-filter settings to update the pll bandwidth in real time. table 5?12 lists the possible settings for charge pump current ( icp ) values for stratix iv plls. table 5?13 lists the possible settings for loop-filter resistor ( r ) values for stratix iv plls. table 5?14 lists the possible settings for loop-filter capacitor ( c ) values for stratix iv plls. table 5?12. charge pump current bit settings cp[2] cp[1] cp[0] decimal value for setting 000 0 001 1 011 3 111 7 table 5?13. loop-filter resistor bit settings lfr[4] lfr[3] lfr[2] lfr[1] lfr[0] decimal value for setting 00000 0 00011 3 00100 4 01000 8 10000 16 10011 19 10100 20 11000 24 11011 27 11100 28 11110 30 table 5?14. loop-filter capacitor bit settings lfc[1] lfc[0] decimal value for setting 00 0 01 1 11 3 chapter 5: clock networks and plls in stratix iv devices 5?51 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 bypassing a pll bypassing a pll counter results in a multiply ( m counter) or a divide ( n and c0 to c9 counters) factor of one. table 5?15 lists the settings for bypassing the counters in stratix iv plls. 1 to bypass any of the pll counters, set the bypass bit to 1 . the values on the other bits are ignored. to bypass the vco post-scale counter ( k ), set the corresponding bit to 0 . dynamic phase-shifting the dynamic phase-shifting feature allows the output phases of individual pll outputs to be dynamically adjusted relative to each other and to the reference clock, without having to send serial data throug h the scan chain of the corresponding pll. this feature simplifies the interface and allo ws you to quickly adjust the clock-to-out ( t co ) delays by changing the output clock phase-shift in real time. this adjustment is achieved by incrementing or decrementing the vco phase-tap selection to a given c counter or to the m counter. the phase is shifted by 1/8 of the vco frequency at a time. the output clocks are active duri ng this phase-reconfiguration process. table 5?16 lists the control signals that are used for dynamic phase-shifting. table 5?15. pll counter settings pll scan chain bits [0..8] settings lsb msb description x xxxxxxx1 (1) pll counter bypassed x xxxxxxx0 (1) pll counter not bypassed because bit 8 (msb) is set to 0 note to table 5?15 : (1) counter-bypass bit. table 5?16. dynamic phase-shifting control signals (part 1 of 2) signal name description source destination phasecounterselect [3..0] counter select. four bits decoded to select either the m or one of the c counters for phase adjustment. one address maps to select all c counters. this signal is registered in the pll on the rising edge of scanclk . logic array or i/o pins pll reconfiguration circuit phaseupdown selects dynamic phase shift direction; 1 = up; 0 = down. signal is registered in the pll on the rising edge of scanclk . logic array or i/o pin pll reconfiguration circuit phasestep logic high enables dynamic phase shifting. logic array or i/o pin pll reconfiguration circuit 5?52 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 table 5?17 lists the pll counter selection based on the corresponding phasecounterselect setting. to perform one dynamic phase-shift, follow these steps: 1. set phaseupdown and phasecounterselect as required. 2. assert phasestep for at least two scanclk cycles. each phasestep pulse enables one phase shift. 3. deassert phasestep after phasedone goes low. 4. wait for phasedone to go high. 5. repeat steps 1-4 as many times as requ ired to perform multiple phase-shifts. the phaseupdown and phasecounterselect signals are synchronous to scanclk and must meet tsu/th requirements with respect to scanclk edges. scanclk free running clock from the core used in combination with phasestep to enable and disable dynamic phase shifting. shared with scanclk for dynamic reconfiguration. gclk, rclk or i/o pin pll reconfiguration circuit phasedone when asserted, this indicates to core-logic that the phase adjustment is complete and the pll is ready to act on a possible second adjustment pulse. asserts based on internal pll timing. de-asserts on the rising edge of scanclk . pll reconfiguration circuit logic array or i/o pins table 5?16. dynamic phase-shifting control signals (part 2 of 2) signal name description source destination table 5?17. phase counter select mapping phasecounterselect[3] [2] [1] [0] selects 0 0 0 0 all output counters 0 001 m counter 0 010 c0 counter 0 011 c1 counter 0 100 c2 counter 0 101 c3 counter 0 110 c4 counter 0 111 c5 counter 1 000 c6 counter 1 001 c7 counter 1 010 c8 counter 1 011 c9 counter chapter 5: clock networks and plls in stratix iv devices 5?53 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 1 you can repeat dynamic phase-shifting inde finitely. for example, in a design where the vco frequency is set to 1000 mhz and the output clock frequency is 100 mhz, performing 40 dynamic phase shifts (each on e yields 125 ps phase shift) results in shifting the output clock by 180, which is a phase shift of 5 ns. the phasestep signal is latched on the negative edge of scanclk (a,c) and must remain asserted for at least two scanclk cycles. de-assert phasestep after phasedone goes low. on the second scanclk rising edge (b,d) after phasestep is latched, the values of phaseupdown and phasecounterselect are latched and the pll starts dynamic phase-shifting for the specified counters and in the indicated direction. phasedone is de-asserted synchronous to scanclk at the second rising edge (b,d) and remains low until the pll finishes dynamic phase- shifting. depending on the vco and scanclk frequencies, phasedone low time may be greater than or less than one scanclk cycle. you can perform another dynamic phase-shift after the phasedone signal goes from low to high. each phasestep pulse enables one phase shift. phasestep pulses must be at least one scanclk cycle apart. depending on the vco and scanclk frequencies, phasedone low time may be greater than or less than one scanclk cycle. after phasedone goes from low to high, you can pe rform another dynamic phase shift. phasestep pulses must be at least one scanclk cycle apart. f for information about the altpll_reconfig megawizard plug-in manager, refer to the phase-locked loops reconfiguration (altpll_reconfig) megafunction user guide . figure 5?43. dynamic phase shifting waveform scanclk phasestep phaseupdown phasedone t phasedone goes low synchronous with scanclk ab c d phasecounterselect configphase 5?54 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 pll specifications f for information about pll timing specifications, refer to the dc and switching characteristics for stratix iv devices chapter. document revision history table 5?18 lists the revision history for this chapter. table 5?18. document revision history (part 1 of 2) date version changes september 2012 3.4 updated the ?periphery clock networks? section. december 2011 3.3 updated the ?dynamic phase-shifting? section. updated figure 5?43. february 2011 3.2 updated the ?clock input connections to the plls,? ?pll clock i/o pins,? ?clock feedback modes,? and ?clock switchover? sections. updated table 5?4 and table 5?8. updated figure 5?26, figure 5?40, and figure 5?43. applied new template. minor text edits. march 2010 3.1 updated table 5?3. updated notes to figure 5?2, figure 5?3, figure 5?4, and figure 5?9. added a note to table 5?5 and table 5?6. added two notes to table 5?4. updated figure 5?43. updated the ?dynamic phase-shifting? section. minor text edits. november 2009 3.0 updated table 5?1 and table 5?7. updated ?clock networks in stratix iv devi ces?, ?periphery clock networks?, and ?cascading plls? sections. added figure 5?5, figure 5?6, figure 5?7, figure 5?8, and figure 5?9. added ?clock sources per region? section. updated figure 5?40. removed ep4se110, ep4se290, and ep4se680 devices. added ep4s40g2, ep4s100g2, ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, and ep4se820 devices. june 2009 2.3 updated table 5?7. updated the ?pll reconfiguration hardware implementation? and ?zero-delay buffer mode? sections. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. chapter 5: clock networks and plls in stratix iv devices 5?55 plls in stratix iv devices september 2012 altera corporation stratix iv device handbook volume 1 april 2009 2.2 updated table 5?1 and table 5?7. updated figure 5?3 and figure 5?4. updated the ?periphery clock networks? section. march 2009 2.1 updated table 5?7. updated figure 5?34. updated ?guidelines? section. removed ?referenced documents? section. november 2008 2.0 updated table 5?7. updated note 1 of figure 5?10. updated figure 5?15. updated figure 5?20 . added figure 5?21 . made minor editorial changes. may 2008 1.0 initial release. table 5?18. document revision history (part 2 of 2) date version changes 5?56 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook september 2012 altera corporation volume 1 september 2012 altera corporation stratix iv device handbook volume 1 section ii. i/o interfaces this section provides information on stratix ? iv device i/o features, external memory interfaces, and high-speed differential interfaces with dpa. this section includes the following chapters: chapter 6, i/o features in stratix iv devices chapter 7, external memory interfaces in stratix iv devices chapter 8, high-speed differential i/o in terfaces and dpa in stratix iv devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. ii?2 section ii: i/o interfaces stratix iv device handbook september 2012 altera corporation volume 1 siv51006-3.4 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 september 2012 feedback subscribe iso 9001:2008 registered 6. i/o features in stratix iv devices this chapter describes how stratix ? iv devices provide i/o capabilities that allow you to work in compliance with current and emerging i/o standards and requirements. with these device features, you can reduce board design interface costs and increase development flexibility. altera ? stratix iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applicatio ns, allowing you to innovate without compromise. stratix iv i/os are specifically designed for ease-of-use and rapid system integration while simultaneously providing the high bandwidth required to maximize internal logic ca pabilities and produce sy stem-level performance. stratix iv device i/o capability far ex ceeds the i/o bandwidth available from previous generation fpgas. independen t modular i/o banks with a common bank structure for vertical migration lend efficiency and flexibility to the high-speed i/o. package and die enhancements with dynamic termination and output control provide best-in-class signal integrity. numerous i/o features assist high-speed data transfer into and out of the device, including: up to 32 full-duplex clock data recove ry (cdr)-based transceivers supporting data rates between 600 mbps and 8.5 gbps dedicated circuitry to support physical layer functionality for popular serial protocols, such as pci express ? (pipe) (pcie) gen1 an d gen2, gigabit ethernet (gbe), serial rapidio ? , sonet/sdh, xaui/higig, (oif) cei-6g, sd/hd/3g-sdi, fibre channel, sfi-5, and interlaken complete pcie protocol solution with embedded pcie hard ip blocks that implement phy-mac layer, data link layer, and transaction layer functionality single-ended, non-voltage-referenced, and voltage-referenced i/o standards low-voltage differential si gnaling (lvds), reduced swing differential signaling (rsds), mini-lvds, high-speed transceiver logic (hstl), and sstl single data rate (sdr) and half data rate (hdr?half frequency and twice data width of sdr) input and output options up to 132 full duplex 1.6 gbps true lvds channels (132 tx + 132 rx) on the row i/o banks hard dynamic phase alignment (dpa) block with serializer/deserializer (serdes) deskew, read and write leveling, and clock-domain crossing functionality programmable output current strength programmable slew rate september 2012 siv51006-3.4 6?2 chapter 6: i/o features in stratix iv devices i/o standards support stratix iv device handbook september 2012 altera corporation volume 1 programmable delay programmable bus-hold circuit programmable pull-up resistor open-drain output serial, parallel, and dynami c on-chip termination (oct) differential oct programmable pre-emphasis programmable equalization programmable differential output voltage (v od ) this chapter contains the following sections: ?i/o standards support? ?i/o banks? on page 6?5 ?i/o structure? on page 6?17 ?on-chip termination support and i/o termination schemes? on page 6?24 ?oct calibration? on page 6?32 ?termination schemes for i/o standards? on page 6?38 ?design considerations? on page 6?46 i/o standards support stratix iv devices support a wide range of industry i/o standards. table 6?1 lists the i/o standards stratix iv devices support, as well as the typical applications. these devices support v ccio voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 v. table 6?1. i/o standards and applications for stratix iv devices (part 1 of 2) i/o standard application 3.3-v lvttl/lvcmos (1) , (2) general purpose 2.5-v lvcmos general purpose 1.8-v lvcmos general purpose 1.5-v lvcmos general purpose 1.2-v lvcmos general purpose 3.0-v pci/pci-x pc and embedded system sstl-2 class i and ii ddr sdram sstl-18 class i and ii ddr2 sdram sstl-15 class i and ii ddr3 sdram hstl-18 class i and ii qdrii/rldram ii hstl-15 class i and ii qdrii/qdrii+/rldram ii hstl-12 class i and ii general purpose differential sstl-2 class i and ii ddr sdram differential sstl-18 class i and ii ddr2 sdram chapter 6: i/o features in stratix iv devices 6?3 i/o standards support september 2012 altera corporation stratix iv device handbook volume 1 f for more information about transceiver supported i/o standards, refer to the transceiver architecture in stratix iv devices chapter. i/o standards an d voltage levels stratix iv devices support a wide range of industry i/o standards, including single-ended, voltage-refere nced single-ended, and differential i/o standards. table 6?2 lists the supported i/o standards and typical values for input and output v ccio , v ccpd , v ref , and board v tt . differential sstl-15 class i and ii ddr3 sdram differential hstl-18 class i and ii clock interfaces differential hstl-15 class i and ii clock interfaces differential hstl-12 class i and ii clock interfaces lvds high-speed communications rsds flat panel display mini-lvds flat panel display lvpecl video graphics and clock distribution notes to table 6?1 : (1) the 3.3-v lvttl/lvcmos standard is supported using v ccio at 3.0 v. (2) for more information ab out the 3.3-v lvttl/lvcmos standard su pported in stratix iv devices, refer to ?3.3-v i/o interface? on page 6?19 . table 6?1. i/o standards and applications for stratix iv devices (part 2 of 2) i/o standard application table 6?2. i/o standards and voltage levels for stratix iv devices (1) (part 1 of 3) i/o standard standard support v ccio (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks 3.3-v lvttl jesd8-b 3.0/2.5 3.0/2.5 3.0 3.0 3.0 ? ? 3.3-v lvcmos (3) jesd8-b 3.0/2.5 3.0/2.5 3.0 3.0 3.0 ? ? 2.5-v lvcmos jesd8-5 3.0/2.5 3.0/2.5 2.5 2.5 2.5 ? ? 1.8-v lvcmos jesd8-7 1.8/1.5 1.8/1.5 1.8 1.8 2.5 ? ? 1.5-v lvcmos jesd8-11 1.8/1.5 1.8/1.5 1.5 1.5 2.5 ? ? 1.2-v lvcmos jesd8-12 1.2 1.2 1.2 1.2 2.5 ? ? 3.0-v pci pci rev 2.1 3.0 3.0 3.0 3.0 3.0 ? ? 3.0-v pci-x pci-x rev 1.0 3.0 3.0 3.0 3.0 3.0 ? ? sstl-2 class i jesd8-9b (2) (2) 2.5 2.5 2.5 1.25 1.25 sstl-2 class ii jesd8-9b (2) (2) 2.5 2.5 2.5 1.25 1.25 sstl-18 class i jesd8-15 (2) (2) 1.8 1.8 2.5 0.90 0.90 sstl-18 class ii jesd8-15 (2) (2) 1.8 1.8 2.5 0.90 0.90 6?4 chapter 6: i/o features in stratix iv devices i/o standards support stratix iv device handbook september 2012 altera corporation volume 1 sstl-15 class i ? (2) (2) 1.5 1.5 2.5 0.75 0.75 sstl-15 class ii ? (2) (2) 1.5 ? 2.5 0.75 0.75 hstl-18 class i jesd8-6 (2) (2) 1.8 1.8 2.5 0.90 0.90 hstl-18 class ii jesd8-6 (2) (2) 1.8 1.8 2.5 0.90 0.90 hstl-15 class i jesd8-6 (2) (2) 1.5 1.5 2.5 0.75 0.75 hstl-15 class ii jesd8-6 (2) (2) 1.5 ? 2.5 0.75 0.75 hstl-12 class i jesd8-16a (2) (2) 1.2 1.2 2.5 0.6 0.6 hstl-12 class ii jesd8-16a (2) (2) 1.2 ? 2.5 0.6 0.6 differential sstl-2 class i jesd8-9b (2) (2) 2.5 2.5 2.5 ? 1.25 differential sstl-2 class ii jesd8-9b (2) (2) 2.5 2.5 2.5 ? 1.25 differential sstl-18 class i jesd8-15 (2) (2) 1.8 1.8 2.5 ? 0.90 differential sstl-18 class ii jesd8-15 (2) (2) 1.8 1.8 2.5 ? 0.90 differential sstl-15 class i ? (2) (2) 1.5 1.5 2.5 ? 0.75 differential sstl-15 class ii ? (2) (2) 1.5 ? 2.5 ? 0.75 differential hstl-18 class i jesd8-6 (2) (2) 1.8 1.8 2.5 ? 0.90 differential hstl-18 class ii jesd8-6 (2) (2) 1.8 1.8 2.5 ? 0.90 differential hstl-15 class i jesd8-6 (2) (2) 1.5 1.5 2.5 ? 0.75 differential hstl-15 class ii jesd8-6 (2) (2) 1.5 ? 2.5 ? 0.75 differential hstl-12 class i jesd8-16a (2) (2) 1.2 1.2 2.5 ? 0.60 differential hstl-12 class ii jesd8-16a (2) (2) 1.2 ? 2.5 ? 0.60 lvds (4) , (5) , (8) ansi/tia/ eia-644 (2) (2) 2.5 2.5 2.5 ? ? rsds (6) , (7) , (8) ? (2) (2) 2.5 2.5 2.5 ? ? mini-lvds (6) , (7) , (8) ? (2) (2) 2.5 2.5 2.5 ? ? table 6?2. i/o standards and voltage levels for stratix iv devices (1) (part 2 of 3) i/o standard standard support v ccio (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks chapter 6: i/o features in stratix iv devices 6?5 i/o banks september 2012 altera corporation stratix iv device handbook volume 1 f for more information about the electrical char acteristics of each i/o standard, refer to the dc and switching ch aracteristics for stratix iv devices chapter. i/o banks stratix iv devices contain up to 24 i/o banks, as shown in figure 6?1 and figure 6?2 . the row i/o banks contain true differential input and output buffers and dedicated circuitry to support differential standards at speeds up to 1.6 gbps. each i/o bank in stratix iv devices can su pport high-performance external memory interfaces with dedicated circuitry. the i/o pins are organized in pairs to support differential standards. each i/o pin pair can support both differential input and output buffers. the only exceptions are the clk[1,3,8,10] , pll_l[1,4]_clk , and pll_r[1,4]_clk pins, which support differential input operations only. f for information about the number of channe ls available for the lvds i/o standard, refer to the high-speed differential i/o interfac e and dpa in stratix iv devices chapter. for more information about transceiver-bank-related features, refer to the transceiver architecture in stratix iv devices chapter. lvpecl ? (4) 2.5 ? ? 2.5 ? ? notes to table 6?2 : (1) v ccpd is either 2.5 or 3.0 v. for v ccio = 3.0 v, v ccpd = 3.0 v. for v ccio = 2.5 v or less, v ccpd = 2.5 v. (2) single-ended hstl/sstl, differential sstl/hstl , and lvds input buffers are powered by v ccpd . row i/o banks support both true differential input buffers and true differential output buffers. column i/o banks support true di fferential input buffers , but not true diff erential output buffers. i/o pins are organized in pairs to support differential standard s. column i/o differential hstl and sstl inputs use lvds differ ential input buffers without on-chip r d support. (3) for more information about the 3.3-v lvttl/lvcmos standard supported in stratix iv devices, refer to ?3.3-v i/o interface? on page 6?19 . (4) column i/o banks support lvpecl i/o standards for input cl ock operation. clock inputs on column i/os are powered by v ccclkin when configured as differential clock inputs. they are powered by v ccio when configured as single-e nded clock inputs. differentia l clock inputs in row i/os are powered by v ccpd . (5) column and row i/o banks support lvds outputs using two single-ended output buffers, an external one-resistor (lvds_e_1r), a nd a three-resistor (lvds_e_3r) network. (6) row i/o banks support rsds and mini-lvds i/o standards using a true lvds output buffe r without a resistor network. (7) column and row i/o banks support rsds and mini-lvds i/o standards using two single-ended output buffers with one-resistor (r sds_e_1r and mini-lvds_e_1r) and three-resistor (rsds_e_3r and mini-lvds_e_3r) networks. (8) the emulated differential outp ut standard that supports the tri-state featur e includes: lvds_e_1r, lvds_e_3r, rsds_e_1r, rsd s_e_3r, mini_lvds_e_1r, and mini_lvds_e_3r. for more information, refer to the i/o buffer (altiobuf) megafunction user guide . table 6?2. i/o standards and voltage levels for stratix iv devices (1) (part 3 of 3) i/o standard standard support v ccio (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks 6?6 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook september 2012 altera corporation volume 1 figure 6?1. stratix iv e devices i/0 banks (1) , (2) , (3) , (4) , (5) , (6) , (7) , (8) notes to figure 6?1 : (1) differential hstl and sstl outputs are not true differential outputs. they use two single-ended outputs with the second outp ut programmed as inverted. (2) column i/o differential hstl and sstl inputs use lvds differential input buffers without differential oct support. (3) column i/o supports lvds outputs using single -ended buffers and external resistor networks. (4) column i/o supports pci/pci-x with on-chip clamp diod e. row i/o supports pci/pci-x with external clamp diode. (5) clock inputs on column i/os are powered by v ccclkin when configured as differential clock inputs. they are powered by v ccio when configured as single-ended clock inputs. all outputs use the corresponding bank v ccio . (6) row i/o supports the true lvds output buffer. (7) column and row i/o banks support lvpe cl standards for i nput clock operation. (8) figure 6?1 is a top view of the si licon die that corres ponds to a reverse view fo r flip chip packages. it is a graphical re presentation o nly. bank 1a bank 8a bank 1c bank 1b bank 2c bank 2a bank 2b bank 8b bank 7b bank 7a bank 7c bank 8c bank 3a bank 3b bank 4b bank 4a bank 4c bank 3c bank 6a bank 6c bank 6b bank 5c bank 5a bank 5b i/o banks 8a, 8b, and 8c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. i/o banks 7a, 7b, and 7c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. i/o banks 3a, 3b, and 3c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. i/o banks 4a, 4b, and 4c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. row i/o banks support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, 1.2-v, sstl-2 class i & ii, sstl-18 class i & ii, sstl-15 class i, hstl-18 class i & ii, hstl-15 class i, hstl-12 class i, lvds, rsds, mini-lvds, differential sstl-2 class i & ii, differential sstl-18 class i & ii, differential sstl-15 class i, differential hstl-18 class i & ii, differential hstl-15 class i, and differential hstl -12 class i standards for input and output operations. lvpecl i/o standard for input operation on dedicated clock input pins. sstl-15 class ii, hstl-15 class ii, hstl-12 class ii, differential sstl-15 class ii, differential hstl-15 class ii, differential hstl-12 class ii standards are only supported for input operations. chapter 6: i/o features in stratix iv devices 6?7 i/o banks september 2012 altera corporation stratix iv device handbook volume 1 figure 6?2. stratix iv gx devices i/o banks (1) , (2) , (3) , (4) , (5) , (6) , (7) , (8) , (9) notes to figure 6?2 : (1) differential hstl and sstl outputs are not true differential outputs. they use two single-ended outputs with the second outp ut programmed as inverted. (2) column i/o differential hstl and sstl inputs use lvds differential input buffers without differential oct support. (3) column i/o supports lvds outputs using single -ended buffers and external resistor networks. (4) column i/o supports pci/pci-x with an on-chip clamp diod e. row i/o supports pci/pci-x with an external clamp diode. (5) clock inputs on column i/os are powered by v ccclkin when configured as differential clock inputs. they are powered by v ccio when configured as single-ended clock inputs. all outputs use the corresponding bank v ccio . (6) row i/o supports the true lvds output buffer. (7) column and row i/o banks support lvpe cl standards for i nput clock operation. (8) figure 6?2 is a top view of the si licon die that corres ponds to a reverse view fo r flip chip packages. it is a graphical re presentation o nly. (9) stratix iv devices do not su pport the pci clamp diode when v ccio is 1.2 v, 1.5 v, or 1.8 v. bank 3a bank 3b bank 4b bank 4a bank 4c bank 3c i/o banks 8a, 8b & 8c support all single-ended and differential input and output operation. i/o banks 7a, 7b & 7c support all single-ended and differential input and output operation. i/o banks 3a, 3b & 3c support all single-ended and differential input and output operation. i/o banks 4a, 4b & 4c support all single-ended and differential input and output operation. bank 1a bank 1c bank 2c bank 2b bank 2a bank 5a bank 5b bank5c bank 6c bank 6a transceiver bank gxbr3 transceiver bank gxbr2 transceiver bank gxbr1 transceiver bank gxbr0 transceiver bank gxbl3 transceiver bank gxbl2 transceiver bank gxbl1 transceiver bank gxbl0 row i/o banks support lvttl, lvcmos, 2.5-v, 1.8- v, 1.5-v, 1.2-v, sstl-2 class i & ii, sstl-18 class i & ii, sstl-15 class i, hstl-18 class i & ii, hstl-15 class i, hstl-12 class i, lvds, rsds, mini-lvds, differential sstl-2 class i & ii, differential sstl-18 class i & ii, differential sstl-15 class i, differential hstl-18 class i & ii, differential hstl-15 class i and differential hstl-12 class i standards for input and output operation. sstl-15 class ii, hstl-15 class ii, hstl-12 class ii, differential sstl-15 class ii, differential hstl-15 class ii, differential hstl-12 class ii standards are only supported for input operations bank 1b bank 6b bank 8a bank 8b bank 7b bank 7a bank 7c bank 8c 6?8 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook september 2012 altera corporation volume 1 modular i/o banks the i/o pins in stratix iv devices are arranged in groups called modular i/o banks. depending on device densities, the number of stratix iv device i/o banks range from 16 to 24. the number of i/o pins on each bank is 24, 32, 36, 40, or 48. figure 6?4 through figure 6?16 show the number of i/o pins available in each i/o bank. in stratix iv devices, the maximum number of i/o banks per side is either four or six, depending on the device density. when migrating between devices with a different number of i/o banks per side, it is the middle or ?b? bank that is removed or inserted. for example, when moving from a 24-bank device to a 16-bank device, the banks that are dropped are ?b? banks, na mely: 1b, 2b, 3b, 4b, 5b, 6b, 7b, and 8b. similarly, when moving from a 16-bank devi ce to a 24-bank device, the banks that are added are the same ?b? banks. after migration from a smaller device to a larger device, the bank size increases or remains the same, but never decreases. for example, the number of i/o pins to a bank may increase from 24 to 26, 32, 36, 40, 42, or 48, but will never decrease. this is shown in figure 6?3 . figure 6?3. bank migration path with increasing device size 24 26 32 36 40 42 48 chapter 6: i/o features in stratix iv devices 6?9 i/o banks september 2012 altera corporation stratix iv device handbook volume 1 figure 6?4 through figure 6?16 show the number of i/o pins and packaging information for different sets of available devices. they show the top view of the silicon die that corresponds to a reverse view for flip chip packages. they are graphical representations only. 1 for figure 6?4 through figure 6?16 , the pin count includes all general purpose i/os, dedicated clock pins, and dual purpose configuration pins. transceiver pins and dedicated configuration pins are not included in the pin count. figure 6?4. number of i/os in each bank in ep4se230 and ep4se360 devices in the 780-pin fineline bga package ep4se230 ep4se360 bank 7a 40 bank 7c 24 26 bank 1c 26 bank 2c 40 bank 4a 24 bank 4c bank 5c 26 32 bank 2a bank 8c 24 bank 8a 40 24 bank 3c 40 bank 3a bank 5a 32 bank 6a 32 bank name number of i/os bank name number of i/os 32 bank 1a bank 6c 26 figure 6?5. number of i/os in each bank in ep4se360, ep4se530, and ep4se820 devices in the 1152-pin fineline bga package ep4se360 ep4se530 ep4se820 bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 42 bank 1c 42 bank 2c 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 6c 42 bank 5c 42 48 bank 2a bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank 5a 48 bank 6a 48 bank name number of i/os bank name number of i/os 48 bank 1a 6?10 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook september 2012 altera corporation volume 1 figure 6?6. number of i/os in each bank in ep4se530 and ep4se820 devices in the 1517-pin fineline bga package ep4se530 ep4se820 bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 42 bank 1c 24 bank 1b 24 bank 2b 42 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 6c 42 bank 6b 24 bank 5b 24 bank 5c 42 50 bank 1a 50 bank 2a bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a bank 5a 50 bank 6a 50 bank name number of i/os bank name number of i/os figure 6?7. number of i/os in each bank in ep4se530 and ep4se820 devices in the 1760-pin fineline bga package ep4se530 ep4se820 bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 48 50 bank 1c 36 bank 1b 36 bank 2b 50 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 48 bank 4c bank 6c 50 bank 6b 36 bank 5b 36 bank 5c 50 50 bank 1a 50 bank 2a bank 8c 48 bank 8a 48 48 bank 3c 48 bank 3a bank 5a 50 bank 6a 50 bank name number of i/os bank name number of i/os chapter 6: i/o features in stratix iv devices 6?11 i/o banks september 2012 altera corporation stratix iv device handbook volume 1 figure 6?8. number of i/os in each bank in ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga package bank 7a 40 bank 7c 24 26 bank 1c 26 bank 2c 40 bank 4a 24 bank 4c 32 bank 2a bank 8c 24 bank 8a 40 24 bank 3c 40 bank 3a bank name number of i/os bank name number of i/os 32 bank 1a number of transceiver channels bank gxbr0 4 4 bank gxbr1 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 figure 6?9. number of i/os in each bank in ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga package 40 bank 4a 32 bank 4c 32 bank 3c 40 bank 3a 4 4 4 4 number of i/os bank name number of transceiver channels bank name number of i/os bank gxbr1 bank gxbr0 bank gxbl1 bank gxbl0 number of transceiver channels bank 1c bank 7a 40 bank 7c 32 bank 8c 32 bank 8a 40 1 ep4sgx290 ep4sgx360 6?12 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook september 2012 altera corporation volume 1 figure 6?10. number of i/os in each bank in ep4sgx70 and ep4sgx110 devices in the 1152-pin fineline bga package bank 7a 40 bank 7c 24 40 bank 4a 24 bank 4c bank 8c 24 bank 8a 40 24 bank 3c 40 bank 3a bank name number of i/os number of i/os bank name *number of transceiver channels 4* 4* 4* 4* 32 26 bank 1a bank 1c bank gxbl1 bank gxbl0 bank gxbr1 bank gxbr0 bank 6a bank 6c 32 26 ep4sgx70 ep4sgx110 figure 6?11. number of i/os in each bank in ep4sgx180, ep4sgx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga package (1) , (2) notes to figure 6?11 : (1) except for the ep4sgx530 device, all list ed devices have two variants in the f1152 package option?one with no pma-only trans ceiver channels and the other with two pma-only transceiver channels for each transceiver bank. the ep4s gx530 device is only offered with two p ma-only transceiver channels for each transcei ver bank in the f1152 package option. (2) there are two additional pma-only trans ceiver channels in each transceiver bank fo r devices with the pma-only transceiver pa ckage option. ep4sgx180 ep4sgx290 ep4sgx360 bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank name number of i/os bank name number of i/os 4 (2) 4 (2) 48 42 bank gxbl1 bank gxbl0 bank 1a bank 1c 48 42 bank gxbr1 bank gxbr0 bank 6a bank 6c ep4sgx230 ep4sgx530 4 (2) 4 (2) chapter 6: i/o features in stratix iv devices 6?13 i/o banks september 2012 altera corporation stratix iv device handbook volume 1 figure 6?12. number of i/os in each bank in ep4sgx180, ep4sgx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga package (1) note to figure 6?12 : (1) there are two additional pma-only trans ceiver channels in each transceiver bank. bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 42 bank 1c 42 bank 2c 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 6c 42 bank 5c 42 48 bank 2a bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank 5a 48 bank 6a 48 bank name number of i/os bank name number of i/os 48 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 6?14 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook september 2012 altera corporation volume 1 figure 6?13. number of i/os in each bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga package (1) note to figure 6?13 : (1) there are two additional pma-only trans ceiver channels in each transceiver bank. ep4sgx530 ep4sgx290 ep4sgx360 bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a number of i/os bank name bank name number of i/os bank 1a bank 1c bank 2c bank 2b bank 2a bank gxbl3 bank gxbl2 bank gxbl1 bank gxbl0 50 50 42 42 20 4 (1) bank 6a bank 6c bank 5c bank 5b bank 5a bank gxbr3 bank gxbr2 bank gxbr1 bank gxbr0 50 50 42 42 20 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) chapter 6: i/o features in stratix iv devices 6?15 i/o banks september 2012 altera corporation stratix iv device handbook volume 1 figure 6?14. number of i/os in each bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga package (1) note to figure 6?14 : (1) there are two additional pma-only trans ceiver channels in each transceiver bank. bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 42 bank 1c 42 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 6c 42 bank 5c 42 50 bank 2a bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a bank 5a 50 bank 6a 50 bank name number of i/os bank name number of i/os 50 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) ep4sgx290 ep4sgx360 ep4sgx530 6?16 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook september 2012 altera corporation volume 1 1 the information in figure 6?15 and figure 6?16 applies to stratix iv gx and gt devices. figure 6?15. number of i/os in each bank in ep4s100g3, ep4s100g4, and ep4s100g5 devices in the 1932-pin fineline bga package (1) note to figure 6?15 : (1) there are two additional pma-only trans ceiver channels in each transceiver bank. bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 21 bank 1c 21 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 6c 22 bank 5c 19 41 bank 2a bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a bank 5a 42 bank 6a 38 bank name number of i/os bank name number of i/os 40 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) 13 bank 2b bank 5b 12 ep4s100g3 ep4s100g4 ep4s100g5 chapter 6: i/o features in stratix iv devices 6?17 i/o structure september 2012 altera corporation stratix iv device handbook volume 1 i/o structure the i/o element (ioe) in stratix iv devices contain a bidirectional i/o buffer and i/o registers to support a complete embedded bidirectional single data rate or ddr transfer. the ioes are located in i/o blocks around the periphery of the stratix iv device. there are up to four ioes per row i/o block and four ioes per column i/o block. the row ioes drive row, column, or direct link interconnects. the column ioes drive column interconnects. the stratix iv bidirectional ioe also supports the following features: programmable input delay programmable output -current strength programmable slew rate programmable output delay programmable bus-hold programmable pull-up resistor open-drain output on-chip series termination with calibration figure 6?16. number of i/os in each bank in ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga package (1) note to figure 6?16 : (1) there are two additional pma-only trans ceiver channels in each transceiver bank. bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 22 bank 1c 23 bank 2c 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 6c 23 bank 5c 23 46 bank 2a bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank 5a 46 bank 6a 44 bank name number of i/os bank name number of i/os 43 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g5 6?18 chapter 6: i/o features in stratix iv devices i/o structure stratix iv device handbook september 2012 altera corporation volume 1 on-chip series termination without calibration on-chip parallel termination with calibration on-chip differential termination pci clamping diode i/o registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output-enable (oe) path for handling the oe signal to th e output buffer. these registers allow faster source-synchronous register-to-register transfers and resynchronization. the input path consists of the ddr input registers, alignment and synchronization registers, and hdr. you can bypass each block of the input path. the output and oe paths are divided into outp ut or oe registers, alignment registers, and hdr blocks. you can bypass each block of the output and oe paths. figure 6?17 shows the stratix iv ioe structure. figure 6?17. ioe structure in stratix iv devices (1) , (2) , (3) , (4) notes to figure 6?17 : (1) the following features are not supported by true differentia l standards: open drain or tri- state output,; programmable curre nt strength and slew rate control; pci clamp; programmable pull-up resistor; bus-hold circuit. (2) the d3_0 and d3_1 delays have the same availa ble settings in the quartus ? ii software (3) one dynamic oct control is available per dq/dqs group. (4) column i/o supports pci/pci-x with an on-chip clamp diod e. row i/o supports pci/pci-x with an external clamp diode. 2 oe from core 4 open drain on-chip termination bus-hold circuit programmable current strength and slew rate control pci clamp v ccio v ccio programmable pull-up resistor half data rate block alignment registers half data rate block write data from core alignment registers 4 half data rate block alignment and synchronization registers prn dq prn dq prn dq prn dq prn dq oe register oe register output register output register clkout to core to core d5, d6 delay input register prn d q input register prn d q input register clkin d5, d6 delay read data to core from oct calibration block d2 delay d3_0 delay d3_1 delay d1 delay output buffer input buffer d5_oct d6_oct firm core dqs logic block dynamic oct control (2) d4 delay dqs cqn chapter 6: i/o features in stratix iv devices 6?19 i/o structure september 2012 altera corporation stratix iv device handbook volume 1 f for more information about i/o register s and how they are used for memory applications, refer to the external memory interfac es in stratix iv devices chapter. 3.3-v i/o interface stratix iv i/o buffers support 3.3-v i/o standards. you can use them as transmitters or receivers in your system. the output high voltage (v oh ), output low voltage (v ol ), input high voltage (v ih ), and input low voltage (v il ) levels meet the 3.3-v i/o standards specifications defined by eia/je dec standard jesd8-b with margin when the stratix iv v ccio voltage is powered by 3.0 v. to ensure device reliability and proper op eration, when interfacing with a 3.3-v i/o system using stratix iv devices, ensure that you do not violate the absolute maximum ratings of the devices. altera recommends performing ibis simulation to determine that the overshoot and undershoot voltages are within the guidelines. when using the stratix iv device as a tran smitter, you can use slow slew rate and series termination to limit ov ershoot and undershoot at the i/o pins, but they are not required. transmission line effects that caus e large voltage deviations at the receiver are associated with an impedance mismatch between the driver and the transmission lines. by matching the impedance of the driver to the characteristic impedance of the transmission line, you can significantly redu ce overshoot voltage. you can use a series termination resistor placed physically clos e to the driver to match the total driver impedance to the transmission line impedance. stratix iv devices support series oct for all lvttl and lvcmos i/o standards in all i/o banks. when using the stratix iv device as a receiv er, you can use a clamping diode (on-chip or off-chip) to limit overshoot, though this is not required. stratix iv devices provide an optional on-chip pci-clamping diode fo r column i/o pins. you can use this diode to protect the i/o pins against overshoot voltage. the 3.3-v i/o standard is support ed using bank supply voltage (v ccio ) at 3.0 v. in this method, the clamping diode (on-chip or off-chip), when enabled, can sufficiently clamp overshoot voltage to within the dc and ac input voltage specifications. the clamped voltage can be expressed as the sum of the supply voltage (v ccio ) and the diode forward voltage. f for more information about the absolute maximum rating and maximum allowed overshoot during transitions, refer to the dc and switching characteristics for stratix iv devices chapter. external memory interfaces in addition to the i/o registers in each ioe, stratix iv devices also have dedicated registers and phase-shift circ uitry on all i/o banks for interfacing with external memory interfaces. f for more information about external memory interfaces, refer to the external memory interfaces in stratix iv devices chapter . 6?20 chapter 6: i/o features in stratix iv devices i/o structure stratix iv device handbook september 2012 altera corporation volume 1 high-speed differential i/o with dpa support stratix iv devices have the following dedicated circuitry for high-speed differential i/o support: differential i/o buffer transmitter serializer receiver deserializer data realignment dynamic phase aligner (dpa) synchronizer (fifo buffer) phase-locked loops (plls) f for more information about dpa support, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. programmable current strength the output buffer for each stratix iv device i/o pin has a programmable current strength control for certain i/o standards. use programmable current strength to mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane. the lvttl, lvcmos, sstl, and hstl standards have several levels of current strength that you can control. table 6?3 lists the programmable current strength for stratix iv devices. table 6?3. programmable current strength (part 1 of 2) (1) , (2) i/o standard i oh / i ol current strength setting (ma) for column i/o pins i oh / i ol current strength setting (ma) for row i/o pins 3.3-v lvttl 16, 12, 8, 4 12, 8, 4 3.3-v lvcmos 16, 12, 8, 4 8, 4 2.5-v lvcmos 16, 12, 8, 4 12, 8, 4 1.8-v lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.2-v lvcmos 8, 6, 4, 2 4, 2 sstl-2 class i 12, 10, 8 12, 8 sstl-2 class ii 16 16 sstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 sstl-18 class ii 16, 8 16, 8 sstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 sstl-15 class ii 16, 8 ? hstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 hstl-18 class ii 16 16 hstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-15 class ii 16 ? chapter 6: i/o features in stratix iv devices 6?21 i/o structure september 2012 altera corporation stratix iv device handbook volume 1 1 altera recommends performing ibis or sp ice simulations to determine the best current strength setting for your specific application. programmable slew rate control the output buffer for each stratix iv device regular- and dual-function i/o pin has a programmable output slew-r ate control that you can configure for low-noise or high-speed performance. a faster slew rate provides high-speed transitions for high-performance systems. a sl ower slew rate can help reduce system noise, but adds a nominal delay to the rising and falling edges. each i/o pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. 1 you cannot use the programmable slew rate feature when using oct. the quartus ii software allows four setti ngs for programmable slew rate control?0, 1, 2, and 3?where 0 is slow slew rate and 3 is fast slew rate. figure 6?4 lists the default slew rate settings from the quartus ii software. you can use faster slew rates to impr ove the available timing margin in memory-interface applications or when th e output pin has high-capacitive loading. 1 altera recommends performing ibis or spice simulations to determine the best slew rate setting for your specific application. hstl-12 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-12 class ii 16 ? notes to table 6?3 : (1) the default setting in th e quartus ii software is 50- ? ? oct r s without calibration for all non-volt age reference and hstl and sstl class i i/o standa rds. the default setting is 25- ? ? oct r s without calibration for hstl and sstl class ii i/o standards. (2) the 3.3-v lvttl and 3.3-v lvcmos are supported using v ccio and v ccpd at 3.0 v. table 6?3. programmable current strength (part 2 of 2) (1) , (2) i/o standard i oh / i ol current strength setting (ma) for column i/o pins i oh / i ol current strength setting (ma) for row i/o pins table 6?4. default slew rate settings i/o standard slew rate option default slew rate 1.2-v, 1.5-v, 1.8-v, 2.5-v lvcmos, and 3.3-v lvttl/lvcmos 0, 1, 2, 3 3 sstl-2, sstl-18, sstl-15, hstl-18, hstl-15, and hstl-12 0, 1, 2, 3 3 3.0-v pci/pci-x 0, 1, 2, 3 3 lvds_e_1r, mini-lvds_e_1r, and rsds_e_1r 0, 1, 2, 3 3 lvds_e_3r, mini-lvds_e_3r, and rsds_e_3r 0, 1, 2, 3 3 6?22 chapter 6: i/o features in stratix iv devices i/o structure stratix iv device handbook september 2012 altera corporation volume 1 programmable i/o delay the following sections describe programmable ioe delay and programmable output buffer delay. programmable ioe delay the stratix iv device ioe includes programmable delays, shown in figure 6?17 on page 6?18 , that you can activate to ensure zero hold times, minimize setup times, or increase clock-to-output times. each pi n can have a different input delay from pin-to-input register or a delay from output register-to-output pin values to ensure that the bus has the same delay going into or out of the device. this feature helps read and time margins because it minimizes the uncertainties between signals in the bus. f for more information about programmable ioe delay specifications, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. programmable output buffer delay stratix iv devices support delay chains built inside the single-ended output buffer, as shown in figure 6?17 on page 6?18 . the delay chains can independently control the rising and falling edge delays of the output buffer, providing the ability to adjust the output-buffer duty cycle, compensate cha nnel-to-channel skew, reduce simultaneous switching output (sso) noise by delibera tely introducing channel-to-channel skew, and improve high-speed memory-interface timing margins. stratix iv devices support four levels of output buffer delay settings. the default setting is no delay . f for more information about programmable output buffer delay specifications, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. open-drain output stratix iv devices provide an optional open -drain output (equivalent to an open collector output) for each i/o pin. when conf igured as open drain, the logic value of the output is either high-z or 0. typically, an external pu ll-up resistor is required to provide logic high. bus hold each stratix iv device i/o pin provides an optional bus-hold feature. bus-hold circuitry can weakly hold the signal on an i/o pin at its last-driven state. because the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated. bus-hold circuitry also pulls non-driven pins away from the input threshold voltage where noise can cause unintended high-fre quency switching. you can select this feature individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent over-driving signals. if you enable the bus-hold feature, you cannot use the programmable pu ll-up option. disable the bus-ho ld feature if the i/o pin is configured for differential signals. bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7k ? to weakly pull the signal level to the last-driven state. chapter 6: i/o features in stratix iv devices 6?23 i/o structure september 2012 altera corporation stratix iv device handbook volume 1 f for more information about the specific sustaining current driven through this resistor and the overdrive current used to identify the next-driven input level, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on th e pin present at the end of configuration. programmable pull-up resistor each stratix iv device i/o pin provides an optional programmabl e pull-up resistor during user mode. if you enable this feat ure for an i/o pin, the pull-up resistor (typically 25 k ) weakly holds the i/o to the v ccio level. programmable pull-up resistors are only supported on user i/o pins and are not supported on dedicated configuration pins, jt ag pins, or dedicated clock pins. if you enable the programmable pull-up option , you cannot use the bus-hold feature. 1 when the optional dev_oe signal drives low, all the i/ o pins remain tri-stated even with the programmable pull-up option enabled. programmable pre-emphasis stratix iv lvds transmitters support prog rammable pre-emphasis to compensate for the frequency dependent attenu ation of the transmission li ne. the quartus ii software allows four settings for programmable pre-emphasis. f for more information about programmable pre-emphasis, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. programmable differential output voltage stratix iv lvds transmitters support programmable v od . the programmable v od settings allow you to adjust output eye height to optimize trace length and power consumption. a higher v od swing improves voltage margins at the receiver end; a smaller v od swing reduces power consumption. the quartus ii software allows four settings for programmable v od . f for more information about programmable v od , refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. multivolt i/o interface the stratix iv architecture supports the multiv olt i/o interface feature that allows the stratix iv devices in all packages to interface with systems of different supply voltages. you can connect the vccio pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-v power supply, depending on the output requirements. the output levels are compatible with systems of the same voltage as the power supply. (for example, when vccio pins are connected to a 1.5-v power supply, the ou tput levels are compatible with 1.5-v systems.) 6?24 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook september 2012 altera corporation volume 1 f for more information about pin connection guidelines, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . the stratix iv vccpd power pins must be connected to a 2.5- or 3.0-v power supply. using these power pins to supply the pre-driver power to the output buffers increases the performance of the output pins. table 6?5 lists stratix iv multivolt i/o support. on-chip termination support and i/o termination schemes stratix iv devices feature dynamic series and parallel oct to provide i/o impedance matching and termination capabilities. oc t maintains signal quality, saves board space, and reduces external component costs. stratix iv devices support: on-chip series termination (r s ) with calibration on-chip series termination (r s ) without calibration on-chip parallel termination (r t ) with calibration dynamic series termination fo r single-ended i/o standards dynamic parallel termination fo r single-ended i/o standards on-chip differential termination (r d ) for differential lvds i/o standards stratix iv devices support oct in all i/o banks by selecting one of the oct i/o standards. these devices also support oct r s and r t in the same i/o bank for different i/o standards if they use the same v ccio supply voltage. you can independently configure each i/o in an i/o bank to support oct r s , programmable current strength, or oct r t . 1 you cannot configure both oct r s and programmable current strength for the same i/o buffer. table 6?5. stratix iv multivolt i/o support (1) v ccio (v) (3) input signal (v) output signal (v) 1.2 1.5 1.8 2.5 3.0 3.3 1.2 1.5 1.8 2.5 3.0 3.3 1.2 y ????? y ????? 1.5 ? y y ???? y ???? 1.8 ? y y ????? y ??? 2.5 ??? yy (2) y (2) ??? y ?? 3.0 ??? y y y ???? y ? notes to table 6?5 : (1) the pin current may be slightly hi gher than the default value. you must verify that the driving device?s v ol maximum and v oh minimum voltages do not violate the applicable stratix iv v il maximum and v ih minimum voltage specifications. (2) altera recommends that you use an external clamping diode on the i/o pins when the input signal is 3.0 v or 3.3 v. you have th e option to use an internal clamping diode for column i/o pins. (3) each i/o bank of a stratix iv device has its own vccio pins and supports only one v ccio , either 1.2, 1.5, 1.8, or 3.0 v. the lvds i/o standard is not supported when v ccio is 3.0 v. the lvds input operations are supported when v ccio is 1.2 v, 1.5 v, 1.8 v, or 2.5 v. the lvds output operations are only supported when v ccio is 2.5 v. chapter 6: i/o features in stratix iv devices 6?25 on-chip termination support and i/o termination schemes september 2012 altera corporation stratix iv device handbook volume 1 a pair of rup and rdn pins are available in a given i/o bank and are shared for series- and parallel-calibrated termination. the rup and rdn pins share the same v ccio and gnd, respectively, with the i/o bank where they are located. the rup and rdn pins are dual-purpose i/os and function as regular i/os if you do not use the calibration circuit. for calibration, the connections are as follows: the rup pin is connected to v ccio through an external 25- ? 1% or 50- ? 1% resistor for an on-chip series termination value of 25- ? ? or 50- ? , respectively. the rdn pin is connected to gnd through an external 25- ? 1% or 50- ? 1% resistor for an on-chip series termination value of 25- ?? or 50- ? , respectively. for on-chip parallel termination, the connections are as follows: the rup pin is connected to v ccio through an external 50- ? 1% resistor. the rdn pin is connected to gnd through an external 50- ? 1% resistor. on-chip series (r s ) termination without calibration stratix iv devices support driver-impedance matching to provide the i/o driver with controlled output impedance that closely matches the impedance of the transmission line. as a result, you can significantly redu ce reflections. stratix iv devices support on-chip series termination for single-ended i/o standards ( figure 6?18 ). the r s shown in figure 6?18 is the intrinsic impedance of the output transistors. typical r s values are 25 ? and 50 ? . when you select matching impedance, current strength is no longer selectable. to use on-chip termination for the sstl class i standard, you must select the 50- ? on-chip series termination setting, thus eliminating the external 25- ? r s (to match the 50- ? transmission line). for the sstl class ii standard, you must select the 25- ? on-chip series termination setting (to match the 50- ? transmission line and the near-end external 50- ? pull-up to v tt ). figure 6?18. on-chip series termination without calibration stratix iv driver series termination receiving device v ccio r s r s gnd = 50 z o 6?26 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook september 2012 altera corporation volume 1 on-chip series termination with calibration stratix iv devices support on-chip series term ination with calibration in all banks. the on-chip series termination calibration circuit compares the total impedance of the i/o buffer to the external 25- ? 1% or 50- ? 1% resistors connected to the rup and rdn pins and dynamically enables or disables the transistors until they match. the r s shown in figure 6?19 is the intrinsic impedance of the transistors. calibration occurs at the end of device configuratio n. when the calibration circuit finds the correct impedance, it powers down and st ops changing the characteristics of the drivers. table 6?6 lists the i/o standards that support on-chip series termination with and without calibration. figure 6?19. on-chip series termination with calibration table 6?6. selectable i/o standards for on-chip series termination with and without calibration (part 1 of 2) i/o standard on-chip series termination setting row i/o ( ? ) column i/o ( ? ) 3.3-v lvttl/lvcmos 50 50 25 25 2.5-v lvcmos 50 50 25 25 1.8-v lvcmos 50 50 25 25 1.5-v lvcmos 50 50 25 1.2-v lvcmos 50 50 25 sstl-2 class i 50 50 sstl-2 class ii 25 25 sstl-18 class i 50 50 sstl-18 class ii 25 25 stratix iv driver series termination receiving device v ccio r s r s gnd = 50 z o chapter 6: i/o features in stratix iv devices 6?27 on-chip termination support and i/o termination schemes september 2012 altera corporation stratix iv device handbook volume 1 left-shift series termination control stratix iv devices support left-shift series termination control. you can use left-shift series termination control to get the calibrated oct r s with half of the impedance value of the external reference resistors connected to the rup and rdn pins. this feature is useful in applications that require both 25- ? and 50- ? calibrated oct r s at the same v ccio . for example, if your application requires 25- ? and 50- ? calibrated oct r s for sstl-2 class i and class ii i/o stan dards, you only need one oct calibration block with 50- ? external reference resistors. you can enable the left-shift series termination control feature in the altiobuf megafunction in the quartus ii software. the quartus ii software only allows left-shift series termination control for 25- ? calibrated oct r s with 50- ? external reference resistors connected to the rup and rdn pins. you can only use left-shift series termination control for the i/o standards that support 25- ? calibrated oct r s . 1 this feature is automatically enabled if you are using a bidirectional i/o with 25- ? calibrated oct r s and 50- ? parallel oct. f for more information about how to enable th e left-shift series termination feature in the altiobuf megafunction, refer to the i/o buffer (altiobuf) megafunction user guide . sstl-15 class i 50 50 sstl-15 class ii ? 25 hstl-18 class i 50 50 hstl-18 class ii 25 25 hstl-15 class i 50 50 hstl-15 class ii ? 25 hstl-12 class i 50 50 hstl-12 class ii ? 25 table 6?6. selectable i/o standards for on-chip series termination with and without calibration (part 2 of 2) i/o standard on-chip series termination setting row i/o ( ? ) column i/o ( ? ) 6?28 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook september 2012 altera corporation volume 1 on-chip parallel termination with calibration stratix iv devices support on-chip parallel te rmination with calibration in all banks. on-chip parallel termination with calibration is only supported for input configuration of input and bidirectional pins. output pin configurations do not support on-chip parallel termination with calibration. figure 6?20 shows on-chip parallel termination with calibration. when you use parallel oct, the v ccio of the bank must match the i/o standard of th e pin where the parallel oct is enabled. the on-chip parallel termination calibration circuit compares the total impedance of the i/o buffer to the external 50- ? 1% resistors connected to the rup and rdn pins and dynamically enables or disables the transistors until they match. calibration occurs at the end of device configuratio n. when the calibration circuit finds the correct impedance, it powers down and st ops changing the characteristics of the drivers. table 6?7 lists the i/o standards that supp ort on-chip parallel termination with calibration. figure 6?20. on-chip parallel termination with calibration table 6?7. selectable i/o standards with on-chip parallel termination with calibration i/o standard on-chip parallel termination setting (column i/o) ( ? ) on-chip parallel termination setting (row i/o) ( ? ) sstl-2 class i, ii 50 50 sstl-18 class i, ii 50 50 sstl-15 class i, ii 50 50 hstl-18 class i, ii 50 50 hstl-15 class i, ii 50 50 hstl-12 class i, ii 50 50 differential sstl-2 class i, ii 50 50 differential sstl-18 class i, ii 50 50 differential sstl-15 class i, ii 50 50 differential hstl-18 class i, ii 50 50 differential hstl-15 class i, ii 50 50 differential hstl-12 class i, ii 50 50 transmitter receiver gnd = 50 z o v ccio 100 100 stratix iv oct v ref chapter 6: i/o features in stratix iv devices 6?29 on-chip termination support and i/o termination schemes september 2012 altera corporation stratix iv device handbook volume 1 expanded on-chip series termi nation with calibration oct calibration circuits always adjust oct r s to match the external resistors connected to the rup and rdn pin; however, it is possible to achieve oct r s values other than the 25- ? and 50- ? resistors. theoretically, if you need a different oct r s value, you can change the re sistance connected to the rup and rdn pins accordingly. practically, the oct r s range that stratix iv devices support is limi ted because of output buffer size and granularity limitations. the quartus ii software only allows discrete oct r s calibration settings of 25, 40, 50, and 60 ? . you can select the closes t discrete value of oct r s with calibration settings in the quartus ii software to your system to achieve the closest timing. for example, if you are using 20- ? oct r s with calibration in your system, you can select the 25- ? oct r s with calibration setting in the quartus ii software to achieve the closest timing. table 6?8 lists expanded oct r s with calibration supported in stratix iv devices. use expanded on-chip series termination wi th calibration of sstl and hstl for impedance matching to improve signal integrity but do not use it to meet the jedec standard. dynamic on-chip termination stratix iv devices support on and off dynami c termination, both series and parallel, for a bidirectional i/o in all i/o banks. figure 6?21 shows the termination schemes supported in stratix iv devices. dynamic pa rallel termination is enabled only when the bidirectional i/o acts as a receiver an d is disabled when it acts as a driver. similarly, dynamic series termination is enabled only when the bidirectional i/o acts as a driver and is disabled when it acts as a receiver. this feature is useful for terminating any high-performance bidirect ional path because signal integrity is optimized depending on the direction of the data. using dynamic oct helps save power because device termination is internal instead of external. termination only switches on during input operation, thus drawing less static power. table 6?8. selectable i/o standards with expanded on-chip series termination with calibration range i/o standard expanded oct r s range row i/o ( ? ) column i/o ( ? ) 3.3-v lvttl/lvcmos 20?60 20?60 2.5-v lvttl/lvcmos 20?60 20?60 1.8-v lvttl/lvcmos 20?60 20?60 1.5-v lvttl/lvcmos 40?60 20?60 1.2-v lvttl/lvcmos 40?60 20?60 sstl-2 20?60 20?60 sstl-18 20?60 20?60 sstl-15 40?60 20?60 hstl-18 20?60 20?60 hstl-15 40?60 20?60 hstl-12 40?60 20?60 6?30 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook september 2012 altera corporation volume 1 1 when using calibrated input parallel and calibrated output series termination on bidirectional pins, they must use the same termination value because each i/o pin can only reference one oct calibration bloc k. the only exception is when using 50 ?? parallel oct and 25 ? series oct using the left shift series termination control. for example, you cannot use calibrated 50 ? parallel oct on the input buffer of a bidirectional pin and calibrated 40 ? series oct on the output buffer because these would require two separate calibration blocks with different rup and rdn resistor values. f for more information about tolerance specific ations for oct with calibration, refer to the dc and switching characteri stics for stratix iv devices chapter. figure 6?21. dynamic parallel oct in stratix iv devices receiver stratix iv oct vccio gnd stratix iv oct transmitter receiver stratix iv oct stratix iv oct transmitter vccio gnd v c c i o g n d g n d v c c i o 100 100 100 100 100 100 100 1 0 0 100 1 0 0 100 1 0 0 100 1 0 0 50 5 0 50 50 50 5 0 = 50 z o = 50 z o chapter 6: i/o features in stratix iv devices 6?31 on-chip termination support and i/o termination schemes september 2012 altera corporation stratix iv device handbook volume 1 lvds input oct (r d ) stratix iv devices support oct for differential lvds input buffers with a nominal resistance value of 100 ? , as shown in figure 6?22 . differential oct r d can be enabled in row i/o banks when both the v ccio and v ccpd is set to 2.5 v . column i/o banks do not support oct r d. dedicated clock input pairs clk[1,3,8,10][p,n] , pll_l[1,4]_clk[p,n] , and pll_r[1,4]_clk[p,n] on the row i/o banks of stratix iv devices do not support r d termination. f for more information about differential on-chip termination, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter . summary of oct assignments table 6?9 lists the oct assignments for the quar tus ii software version 9.1 and later. figure 6?22. differential input oct transmitter receiver 100 = 50 z o = 50 z o table 6?9. summary of oct assignments in the quartus ii software assignment name value applies to input termination parallel 50 ? with calibration input buffers for single-ended and differential hstl/sstl standards differential input buffers for lvds receivers on row i/o banks (1) output termination series 25 ? without calibration output buffers for single-ended lvttl/lvcmos and hstl/sstl standards as well as differential hstl/sstl standards series 50 ? without calibration series 25 ? with calibration series 40 ? with calibration series 50 ? with calibration series 60 ? with calibration note to table 6?9 : (1) you can enable differential oct r d in row i/o banks when both v ccio and v ccpd are set to 2.5 v . 6?32 chapter 6: i/o features in stratix iv devices oct calibration stratix iv device handbook september 2012 altera corporation volume 1 oct calibration stratix iv devices support calibrated on-chip series termination (r s ) and calibrated on-chip parallel termination (r t ) on all i/o pins. you can calibrate the device?s i/o bank with any of the oct calibration blocks available in the device provided the v ccio of the i/o bank with the pins using calibrated oct matches the v ccio of the i/o bank with the calibratio n block and its associated rup and rdn pins. oct calibration block location table 6?10 and table 6?11 list the location of oct calibration blocks in stratix iv devices. for both tables, the following legend applies: ?y? indicates i/o banks with oct calibration block ?n? indicates i/o banks without oct calibration block ??? indicates i/o banks that ar e not available in the device 1 table 6?10 and table 6?11 do not show transceiver banks and transceiver calibration blocks. table 6?10 lists the oct calibration blocks in banks 1a through 4c. table 6?10. oct calibration block counts and placement in stratix iv devices (1a through 4c) (part 1 of 2) device pin number of oct blocks bank 1a 1b 1c 2a 2b 2c 3a 3b 3c 4a 4b 4c ep4se230 780 8 y ? n y ? n y ? n y ? n ep4se360 780 8 y?n y?n y?n y?n 1152 8 y ? n y ? n y n n y n n ep4se530 1152 8 y ? n y ? n y n n y n n 1517 10 y n n y n n y n y y n n 1760 10 y n n y n n y n y y n n ep4se820 1152 8 y ? n y ? n y n n y n n 1517 10 y n n y n n y n y y n n 1760 10 y n n y n n y n y y n n ep4sgx70 780 8 y ? n y ? n y ? n y ? n ep4sgx110 780 8 y?n y?n y?n y?n 1152 8 y ? n ? ? ? y ? n y ? n ep4sgx180 780 8 y?n y?n y?n y?n 1152 8 y ? n ? ? ? y n n y n n 1517 8 y ? n y ? n y n n y n n ep4sgx230 780 8 y?n y?n y?n y?n 1152 8 y ? n ? ? ? y n n y n n 1517 8 y ? n y ? n y n n y n n chapter 6: i/o features in stratix iv devices 6?33 oct calibration september 2012 altera corporation stratix iv device handbook volume 1 table 6?11 lists the oct calibration blocks in banks 5a through 8c. ep4sgx290 780 8 ?????? y ? n y ? n 1152 8 y ? n ? ? ? y n n y n n 1517 8 y ? n y ? n y n n y n n 1760 8 y ? n y ? n y n n y n n 1932 10 y n n y ? n y n y y n n ep4sgx360 780 8 ?????? y ? n y ? n 1152 8 y ? n ? ? ? y n n y n n 1517 8 y ? n y ? n y n n y n n 1760 8 y ? n y ? n y n n y n n 1932 10 y n n y ? n y n y y n n ep4sgx530 1152 8 y ? n ? ? ? y n y y n n 1517 10 y ? n y ? n y n y y n n 1760 10 y ? n y ? n y n y y n n 1932 10 y ? n y n n y n y y n n ep4s40g2 1517 8 y ? n y ? n y n n y n n ep4s40g5 1517 10 y ? n y ? n y n y y n n ep4s100g2 1517 8 y ? n y ? n y n n y n n ep4s100g3 1932 10 y ? n y n n y n y y n n ep4s100g4 1932 10 y ? n y n n y n y y n n ep4s100g5 1517 10 y ? n y ? n y n y y n n 1932 10 y ? n y n n y n y y n n table 6?10. oct calibration block counts and placement in stratix iv devices (1a through 4c) (part 2 of 2) device pin number of oct blocks bank 1a 1b 1c 2a 2b 2c 3a 3b 3c 4a 4b 4c table 6?11. oct calibration block counts and placement in stratix iv devices (5a through 8c) (part 1 of 2) device pin number of oct blocks bank 5a 5b 5c 6a 6b 6c 7a 7b 7c 8a 8b 8c ep4se230 780 8 y ? n y ? n y ? n y ? n ep4se360 780 8 y?n y?n y?n y?n 1152 8 y ? n y ? n y n n y n n ep4se530 1152 8 y ? n y ? n y n n y n n 1517 10 y n n y n n y n n y n y 1760 10 y n n y n n y n n y n y ep4se820 1152 8 y ? n y ? n y n n y n n 1517 10 y n n y n n y n n y n y 1760 10 y n n y n n y n n y n y ep4sgx70 780 8 ?????? y ? n y ? n 6?34 chapter 6: i/o features in stratix iv devices oct calibration stratix iv device handbook september 2012 altera corporation volume 1 sharing an oct calibration block on multiple i/o banks an oct calibration block has the same v ccio as the i/o bank that contains the block. oct r s calibration is supported on all i/o banks with different v ccio voltage standards, up to the number of available oct calibration blocks. you can configure the i/o banks to receive calibration codes from any oct calibration block with the same v ccio . all i/o banks with the same v ccio can share one oct calibration block, even if that particular i/o ba nk has an oct calibration block. ep4sgx110 780 8 ?????? y ? n y ? n 1152 8 ? ? ? y ? n y ? n y ? n ep4sgx180 780 8 ?????? y ? n y ? n 1152 8 ? ? ? y ? n y n n y y n 1517 8 y ? n y ? n y n n y n n ep4sgx230 780 8 ?????? y ? n y ? n 1152 8 ? ? ? y ? n y n n y y n 1517 8 y ? n y ? n y n n y n n ep4sgx290 780 8 ?????? y ? n y ? n 1152 8 ? ? ? y ? n y n n y n n 1517 8 y ? n y ? n y n n y n n 1760 8 y ? n y ? n y n n y n n 1932 10 y ? n y n n y n n y n y ep4sgx360 780 8 ?????? y ? n y ? n 1152 8 ? ? ? y ? n y n n y n n 1517 8 y ? n y ? n y n n y n n 1760 8 y ? n y ? n y n n y n n 1932 10 y ? n y n n y n n y n y ep4sgx530 1152 8 ? ? ? y ? n y n n y n y 1517 10 y ? n y ? n y n n y n y 1760 10 y ? n y ? n y n n y n y 1932 10 y n n y ? n y n n y n y ep4s40g2 1517 8 y ? n y ? n y n n y n n ep4s40g5 1517 10 y ? n y ? n y n n y n y ep4s100g2 1517 8 y ? n y ? n y n n y n n ep4s100g3 1932 10 y n n y ? n y n n y n y ep4s100g4 1932 10 y n n y ? n y n n y n y ep4s100g5 1517 10 y ? n y ? n y n n y n y 1932 10 y n n y ? n y n n y n y table 6?11. oct calibration block counts and placement in stratix iv devices (5a through 8c) (part 2 of 2) device pin number of oct blocks bank 5a 5b 5c 6a 6b 6c 7a 7b 7c 8a 8b 8c chapter 6: i/o features in stratix iv devices 6?35 oct calibration september 2012 altera corporation stratix iv device handbook volume 1 for example, figure 6?23 shows a group of i/o banks that has the same v ccio voltage. if a group of i/o banks has the same v ccio voltage, you can use one oct calibration block to calibrate the group of i/o banks placed around the periphery. because 3b, 4c, 6c, and 7b have the same v ccio as bank 7a, you can calibrate all four i/o banks (3b, 4c, 6c, and 7b) with the oct calibration block (cb7) located in bank 7a. you can enable this by serially shifting out oct r s calibration codes from the oct calibration block located in bank 7a to the i/o banks located around the periphery. 1 i/o banks that do not contain calibration blocks share calibration blocks with i/o banks that do contain calibration blocks. figure 6?23 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. it is a graphical representation only. this figure does not show transceiver banks and transc eiver calibration blocks. oct calibration block modes of operation stratix iv devices support oct r s and oct r t on all i/o banks. the calibration can occur in either power-up or user mode. power-up mode in power-up mode, oct calibration is automatically performed at power up. calibration codes are shifted to selected i/o buffers before transitioning to user mode. figure 6?23. example of calibrating multiple i/o banks with one shared oct calibration block stratix iv bank 8a bank 8c bank 8b bank 7b bank 7c bank 1a bank 1c bank 1b bank 2a bank 2b bank 2c bank 3a bank 3c bank 3b bank 4a bank 4b bank 4c bank 6a bank 6c bank 6b bank 5a bank 5b bank 5c bank 7a cb 7 i/o bank with the same v ccio i/o bank with different v ccio 6?36 chapter 6: i/o features in stratix iv devices oct calibration stratix iv device handbook september 2012 altera corporation volume 1 user mode in user mode, the octusrclk , enaoct , nclrusr , and enaser[9..0] signals are used to calibrate and serially transfer calibration codes from each oct calibration block to any i/o. table 6?12 lists the user-controlled calibration block signal names and their descriptions. figure 6?24 shows the flow of the user signal. when enaoct is 1, all oct calibration blocks are in calibration mode; when enaoct is 0, all oct calibration blocks are in serial data transfer mode. the octusrclk clock frequency must be 20 mhz or less. 1 you must generate all user signals on the rising edge of octusrclk . figure 6?24 does not show transceiver banks and transceiver calibration blocks. table 6?12. oct calibration block ports for user control signal name description octusrclk clock for oct block. enaoct enable oct termination (generated by user ip). enaser[9..0] when enoct = 0, each signal enables the oct serializer for the corresponding oct calibration block. when enaoct = 1, each signal enables oct calibration for the corresponding oct calibration block. s2pena_< bank# > serial-to-parallel load enable per i/o bank. nclrusr clear user. figure 6?24. signals used for user mode calibration bank 8a bank 8c bank 8b bank 7b bank 7c bank 1a bank 1c bank 1b bank 2a bank 2b bank 2c bank 3a bank 3c bank 3b bank 4a bank 4b bank 4c bank 6a bank 6c bank 6b bank 5a bank 5b bank 5c bank 7a stratix iv core s2pena_1c s2pena_6c s2pena_4c cb0 cb9 cb1 cb2 cb4 cb3 cb5 cb6 cb7 cb8 enaoct, nclrusr, octusrclk, enaser[n] chapter 6: i/o features in stratix iv devices 6?37 oct calibration september 2012 altera corporation stratix iv device handbook volume 1 oct calibration figure 6?25 shows user mode signal-timing waveforms. to calibrate oct block[n] (where n is a calibration block number), you must assert enaoct one cycle before asserting enaser[n] . also, nclrusr must be set to low for one octusrclk cycle before the enaser[n] signal is asserted. assert the enaser[n] signals for 1000 octusrclk cycles to perform octrs and octr t calibration. you can de-assert enaoct one clock cycle after the last enaser is de-asserted. serial data transfer after you complete calibration, you must seri ally shift out the 28-bit oct calibration codes (14-bit oct r s and 14-bit oct r t ) from each oct calibration block to the corresponding i/o buffers. only one oct calibration block can send out the codes at any time by asserting only one enaser[n] signal at a time. after you de-assert enaoct , wait at least one octusrclk cycle to enable any enaser[n] signal to begin serial transfer. to shift the 28-bit code from the oct calibration block[n], you must assert enaser[n] for exactly 28 octusrclk cycles. between two consecutive asserted enaser signals, there must be at least one octusrclk cycle gap. ( figure 6?25 ). after calibrated codes are shifted in serial ly to each i/o bank, the calibrated codes must be converted from serial to parallel fo rmat before being used in the i/o buffers. figure 6?25 shows the s2pena signals that can be asserted at any time to update the calibration codes in each i/o bank. all i/ o banks that received the codes from the same oct calibration block can have s2pena asserted at the same time, or at a different time, even while another oct calibration block is calibrating and serially shifting codes. the s2pena signal is asserted one octusrclk cycle after enaser is de-asserted for at least 25 ns. you cannot use i/os for transmitting or receiving data when their s2pena is asserted for parallel codes transfer. figure 6?25. oct user mode signal?timing waveform for one oct block note to figure 6?25 : (1) t s2p ? 25 ns. octusrclk nclrusr enaoct enaser0 calibration phase s2pena_1a 28 octusrclk cycles t s2p (1) 1000 octusrclk cycles 6?38 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook september 2012 altera corporation volume 1 example of using multiple oct calibration blocks figure 6?26 shows a signal timing waveform for two oct calibration blocks doing r s and r t calibration. calibration blocks can start calibrating at different times by asserting the enaser signals at different times. enaoct must remain asserted while any calibration is ongoing. you must set nclrusr low for one octusrclk cycle before each enaser[n] signal is asserted. in figure 6?26 , when you set nclrusr to 0 for the second time to initialize oct calibration block 0, this does not affect oct calibration block 1, whose calibration is already in progress. r s calibration if only r s calibration is used for an oct calibration block, its corresponding enaser signal only requires to be asserted for 240 octusrclk cycles. 1 you must assert the enaser signal for 28 octusrclk cycles for serial transfer. termination schemes for i/o standards the following sections describe the different termination schemes for the i/o standards used in stratix iv devices. single-ended i/o sta ndards termination voltage-referenced i/o standards requir e both an input reference voltage, v ref , and a termination voltage, v tt . the reference voltage of the receiving device tracks the termination voltage of th e transmitting device. figure 6?27 and figure 6?28 show the details of sstl and hstl i/o termination on stratix iv devices. figure 6?26. oct user-mode signal timing waveform for two oct blocks notes to figure 6?26 : (1) ts2p ? 25 ns. (2) s2pena_1a is asserted in bank 1a for calibration block 0. (3) s2pena_2a is asserted in bank 2a for calibration block 1. octusrclk enaoct nclrusr enaser0 enaser1 s2pena_1a (2) s2pena_2a (3) ts2p (1) ts2p (1) calibration phase 1000 cycles octusrclk 1000 cycles octusrclk 28 cycles octusrclk 28 cycles octusrclk chapter 6: i/o features in stratix iv devices 6?39 termination schemes for i/o standards september 2012 altera corporation stratix iv device handbook volume 1 1 in stratix iv devices, you cannot use seri es and parallel oct simultaneously. for more information, refer to ?dynamic on-chip termination? on page 6?29 . figure 6?27. sstl i/o standard termination sstl class i sstl class ii external on-board termination oct transmit oct receive oct in bi- directional pins v tt 50 25 50 v tt 50 25 50 v tt 50 transmitter transmitter receiver receiver v tt 50 50 8 50 transmitter receiver stratix iv series oct 50 v tt 50 50 v tt 50 transmitter receiver 25 stratix iv series oct v ccio 100 25 50 transmitter receiver stratix iv parallel oct 100 v ccio 100 25 50 8 transmitter receiver stratix iv parallel oct 100 v tt 50 v ccio 100 50 stratix iv 100 v ccio 100 100 stratix iv v ref v ref v ref v ref v ref v ref v ref termination series oct 50 series oct 50 v ccio 100 50 stratix iv 100 v ccio 100 100 stratix iv series oct 25 series oct 25 6?40 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook september 2012 altera corporation volume 1 figure 6?28. hstl i/o standard termination hstl class i hstl class ii external on-board termination oct transmit oct receive oct in bi- directional pins v tt 50 50 v tt 50 50 v tt 50 transmitter transmitter receiver receiver v tt 50 50 transmitter receiver v tt 50 50 v tt 50 transmitter receiver v ccio 100 50 transmitter receiver stratix iv parallel oct 100 v ccio 100 50 transmitter receiver stratix iv parallel oct 100 v tt 50 v ccio 100 50 stratix iv 100 v ccio 100 100 stratix iv stratix iv series oct 50 stratix iv series oct 25 v ref v ref v ref v ref v ref v ref termination series oct 50 series oct 50 v ccio 100 50 8 stratix iv 100 v ccio 100 100 stratix iv series oct 25 series oct 25 chapter 6: i/o features in stratix iv devices 6?41 termination schemes for i/o standards september 2012 altera corporation stratix iv device handbook volume 1 differential i/o standards termination stratix iv devices support differential ss tl-18 and sstl-2, differential hstl-18, hstl-15, hstl-12, lvds, lvpecl, rsds, and mini-lvds. figure 6?29 through figure 6?35 show the details of various differenti al i/o terminations on these devices. 1 differential hstl and sstl outputs are not true differential outputs. they use two single-ended outputs with the second output programmed as inverted. figure 6?29. differential sstl i/o standard termination differential sstl class i differential sstl class ii external on-board termination oct transmitter receiver 50 50 50 50 v tt v tt 25 25 transmitter receiver 50 50 50 50 v tt v tt 25 25 50 50 v tt v tt 50 50 termination transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 25 series oct gnd gnd v tt v tt differential sstl class ii transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 50 series oct gnd gnd differential sstl class i 6?42 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook september 2012 altera corporation volume 1 figure 6?30. differential hstl i/o standard termination differential hstl class i differential hstl class ii external on-board termination oct transmitter receiver 50 50 50 50 v tt v tt transmitter receiver 50 50 50 50 v tt v tt 50 50 v tt v tt termination transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 50 series oct gnd gnd differential hstl class i 50 50 transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 25 series oct gnd gnd v tt v tt differential hstl class ii chapter 6: i/o features in stratix iv devices 6?43 termination schemes for i/o standards september 2012 altera corporation stratix iv device handbook volume 1 lvds the lvds i/o standard is a differential high-speed, low-voltage swing, low-power, general-purpose i/o interface standard. in stratix iv devices, the lvds i/o standard requires a 2.5-v v ccio level. the lvds input buffer requires 2.5-v v ccpd . use this standard in applications requiring high-ban dwidth data transfer, such as backplane drivers and clock distribu tion. lvds requires a 100- ? termination resistor between the two signals at the input buffer. stra tix iv devices provide an optional 100- ? differential termination resistor in the device using on-chip differential termination. figure 6?31 shows lvds termination. the on-chi p differential resistor is only available in the row i/o banks. figure 6?31. lvds i/o standard termination (1) notes to figure 6?31 : (1) for lvds output with a three-resistor network, the r s and r p values are 120 and 170 ? , respectively. for lvds output with a one-resistor network, the r p value is 120 ? . (2) side i/o banks support true lvds output buffers. (3) column and side i/o banks support lvds_e_1r and lvds_ e_3r i/o standards using two single-ended output buffers. differential outputs differential inputs 100 single-ended outputs differential inputs 100 rp external resistor single-ended outputs differential inputs 100 rp external resistor rs rs stratix iv oct stratix iv oct stratix iv oct differential outputs differential inputs 100 external on-board termination oct receive (true lvds output) (2) termination lvds 50 50 50 50 50 50 50 50 oct receive (single-ended lvds output with one-resistor network, lvds_e_1r) (3) oct receive (single-ended lvds output with three-resistor network, lvds_e_3r) (3) 1 inch 1 inch 6?44 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook september 2012 altera corporation volume 1 differential lvpecl in stratix iv devices, the lvpecl i/o standa rd is supported on input clock pins on column and row i/o banks. lvpecl output operation is not supported in stratix iv devices. lvds input buffers are used to support lvpecl input operation. ac coupling is required when the lvpecl common-mode voltage of the output buffer is higher than the lvpecl input common-mode voltage. figure 6?32 shows the ac-coupled termination scheme. the 50- ? resistors used at the receiver end are external to the device. dc-coupled lvpecl is supported if the lvpecl output common mode voltage is within the stratix iv lvpecl input buffer specification ( figure 6?33 ). figure 6?32. lvpecl ac-coupled termination (1) note to figure 6?32 : (1) the lvpecl ac-coupled termination is applicable on ly when you use an altera fpga lvpecl transmitter. figure 6?33. lvpecl dc-coupled termination (1) note to figure 6?33 : (1) the lvpecl dc-coupled termination is applicable on ly when you use an altera fpga lvpecl transmitter. altera fpga l v pecl o u tp u t b u ffer stratix i v l v pecl inp u t b u ffer 50 = 50 = 50 0.1 f 0.1 f 50 v icm z o z o altera fpga l v pecl o u tp u t b u ffer stratix i v l v pecl inp u t b u ffer 100 = 50 z o = 50 z o chapter 6: i/o features in stratix iv devices 6?45 termination schemes for i/o standards september 2012 altera corporation stratix iv device handbook volume 1 rsds stratix iv devices support the rsds output standard with data rates up to 230 mbps using lvds output buffer types. for tr ansmitters, use two single-ended output buffers with the external one- or three-resi stor networks in the column i/o bank, as shown in figure 6?34 . the one-resistor topology is for data rates up to 200 mbps. the three-resistor topology is for data rates above 200 mbps. the row i/o banks support rsds output using true lvds output buff ers without an external resistor network. a resistor network is required to attenuat e the lvds output-voltage swing to meet rsds specifications. you can modify the three-resistor network values to reduce power or improve noise margin. the re sistor values chosen must satisfy equation 6?1 . 1 altera recommends performing additional si mulations using ibis models to validate that custom resistor values meet the rsds requirements. f for more information about the rsds i/o standard, refer to the rsds specification from the national semiconductor website at www.national.com . figure 6?34. rsds i/o standard termination (1) note to figure 6?34 : (1) the r s and r p values are pending characterization. 50 50 r s r s r p transmitter receiver 1 inch 50 50 r p transmitter 1 inch 50 50 100 r p transmitter receiver 1 inch 50 50 r s r s r p transmitter receiver 1 inch termination external on-board termination oct one-resistor network (rsds_e_1r) three-resistor network (rsds_e_3r) 100 receiver stratix iv oct stratix iv oct 100 100 equation 6?1. r s r p 2 ------ - ? r s r p 2 ------ - + -------------------- 50 ? = 6?46 chapter 6: i/o features in stratix iv devices design considerations stratix iv device handbook september 2012 altera corporation volume 1 mini-lvds stratix iv devices support the mini-lvds output standard with data rates up to 340 mbps using lvds output buffer types. for transmitters, use two single-ended output buffers with external one- or three-resistor networks, as shown in figure 6?35 . the one-resistor topology is for data rates up to 200 mbps. the three-resistor topology is for data rates above 200 mbps. the row i/o banks support mini-lvds output using true lvds output buffers withou t an external resistor network. a resistor network is required to attenuate the lvds output voltage swing to meet the mini-lvds specifications. you can modify the three-resistor network values to reduce power or improve noise margin. the re sistor values chosen must satisfy equation 6?1 on page 6?45 . 1 altera recommends that you perform additi onal simulations using ibis models to validate that custom resistor va lues meet the rsds requirements. f for more information about the mini-lvds i/o standard, see the mini-lvds specification from the texas instruments website at www.ti.com . design considerations although stratix iv devices feature variou s i/o capabilities for high-performance and high-speed system designs, there are several other design considerations that require your attention to ensure the success of your designs. i/o bank restrictions each i/o bank can simultaneously support multiple i/o standards. the following sections provide guidelines for mixing non- voltage-referenced and voltage-referenced i/o standards in stratix iv devices. figure 6?35. mini-lvds i/o standard termination (1) note to figure 6?35 : (1) the r s and r p values are pending characterization. 50 50 r s r s r p transmitter receiver 1 inch 50 r p transmitter receiver 1 inch 50 50 r p transmitter receiver 1 inch 50 50 r s r s r p transmitter receiver 1 inch termination external on-board termination oct one-resistor network (mini-lvds_e_1r) three-resistor network (mini-lvds_e_3r) 50 100 stratix iv oct stratix iv oct 100 100 100 chapter 6: i/o features in stratix iv devices 6?47 design considerations september 2012 altera corporation stratix iv device handbook volume 1 non-voltage-referenced standards each i/o bank of a stra tix iv device has its own vccio pins and supports only one v ccio , either 1.2, 1.5, 1.8, 2.5, or 3.0 v. an i/o bank can simultaneously support any number of input signals with different i/ o standard assignments if it meets the v ccio and v ccpd requirement, as shown in table 6?2 on page 6?3 . for output signals, a single i/o bank suppo rts non-voltage-referenced output signals that are driving at the same voltage as v ccio . because an i/o bank can only have one v ccio value, it can only drive out that one value for non-voltage- referenced signals. for example, an i/o bank with a 2.5-v v ccio setting can support 2.5-v standard inputs and outputs as well as 3.0-v lvcmos inputs (but not output or bidirectional pins). voltage-referenced standards to accommodate voltage-referenced i/o stan dards, each stratix iv device?s i/o bank supports multiple vref pins feeding a common v ref bus. the number of available vref pins increases as device density increases. if these pins are not used as vref pins, they cannot be used as generic i/o pins and must be tied to v ccio or gnd. each bank can only have a single v ccio voltage level and a single v ref voltage level at a given time. an i/o bank featuring single-ended or differential standards can support voltage-referenced standards if all voltage-referenced standards use the same v ref setting. for performance reasons, voltage-referenced input standards use their own v ccpd level as the power source. this feature allo ws you to place voltage-referenced input signals in an i/o bank with a v ccio of 2.5 v or below. for example, you can place hstl-15 input pins in an i/o bank with 2.5-v v ccio . however, the voltage-referenced input with parallel oct enabled requires the v ccio of the i/o bank to match the voltage of the input standard. voltage-referenced bidirectional and output signals must be the same as the i/o bank?s v ccio voltage. for example, you can only place sstl-2 output pins in an i/o bank with a 2.5-v v ccio . mixing voltage-referenced and non-voltage-referenced standards an i/o bank can support both voltage-refere nced and non-voltage-referenced pins by applying each of the rule sets individual ly. for example, an i/o bank can support sstl-18 inputs and 1.8-v inputs and outputs with a 1.8-v v ccio and a 0.9-v v ref . similarly, an i/o bank can support 1.5-v st andards, 1.8-v inputs (but not outputs), and hstl and hstl-15 i/o standards with a 1.5-v v ccio and 0.75-v v ref . 6?48 chapter 6: i/o features in stratix iv devices design considerations stratix iv device handbook september 2012 altera corporation volume 1 document revision history table 6?13 lists the revision history for this chapter. table 6?13. document revision history (part 1 of 2) date version changes september 2012 3.4 updated the ?programmable slew rate control? section to close fb #68385. updated figure 6?17 to close fb #57979. december 2011 3.3 updated figure 6?2 and figure 6?17. february 2011 3.2 updated the ?modular i/o banks?, ?on-chip termination support and i/o termination schemes?, ?dynamic on-chip termination? , and ?programmable pull-up resistor? sections. updated figure 6?17, figure 6?32, and figure 6?33. applied new template. minor text edits. march 2010 3.1 updated table 6?2 and table 6?5. updated figure 6?18, figure 6?19, figure 6?27, figure 6?28, and figure 6?31. added the ?summary of oct assignments? section. added a note to the ?sharing an oct calibration block on multiple i/o banks? section. updated the ?oct calibration? section. minor text edits. november 2009 3.0 updated table 6?2, table 6?4, table 6?6, table 6?9, and table 6?10. updated figure 6?1, figure 6?2, figure 6?4, figure 6?5, figure 6?6, figure 6?8, figure 6?9, figure 6?10, figure 6?11, fi gure 6?12, figure 6?13, and figure 6?31. added table 6?8. added figure 6?7, figure 6?14, figure 6?15, and figure 6?16. added ?left-shift series termination control? and ?expanded on-chip series termination with calibration? sections. updated ?multivolt i/o interface?, ?rsds?, ?mini-lvds?, and ?non-voltage-referenced standards? sections. deleted figure 6-5: number of i/os in each bank in ep4se290 and ep4se360 in the 1517-pin fineline bga package. minor text edits. june 2009 2.3 added introductory sentences to improve search ability. removed the conclusion section. april 2009 2.2 updated figure 6?2. updated table 6?8 and table 6?9. deleted figure 6-14. march 2009 2.1 updated table 6?1, table 6?2,table 6?3, table 6?4, table 6?6, table 6?8, and table 6?9. updated figure 6?2, figure 6?7, figure 6?8, figure 6?9, figure 6?10, figure 6?11, and figure 6?12. added figure 6?14. removed equation 6?2 and ?referenced documents? section. chapter 6: i/o features in stratix iv devices 6?49 design considerations september 2012 altera corporation stratix iv device handbook volume 1 november 2008 2.0 updated ?modular i/o banks? on page 6?7. updated figure 6?3 and figure 6?21. made minor editorial changes. may 2008 1.0 initial release. table 6?13. document revision history (part 2 of 2) date version changes 6?50 chapter 6: i/o features in stratix iv devices design considerations stratix iv device handbook september 2012 altera corporation volume 1 siv51007-3.2 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 7. external memory interfaces in stratix iv devices this chapter describes external memory interfaces available with the stratix ? iv device family and that family?s silicon capability to support external memory interfaces. to support the level of sy stem bandwidth achi evable with altera ? stratix iv fpgas, the devices provide an effi cient architecture to quickly and easily fit wide external memory interfaces within th eir small modular i/o bank structure. the i/os are designed to provide high-perform ance support for existing and emerging external double data rate (ddr) memory standards, such as ddr3, ddr2, ddr sdram, qdr ii+, qdr ii sram, and rldram ii. stratix iv i/o elements provide easy-to-use built-in functionality required for a rapid and robust implementation with features such as dynamic calibrated on-chip termination (oct), trace mismatch compensa tion, read- and write-leveling circuit for ddr3 sdram interfaces, half data rate (hdr) blocks, and 4- to 36-bit programmable dq group widths. the high-performance memory interface solution is backed-up by a self-calibrating megafunction (altmemphy), optimized to take advantage of the stratix iv i/o structure and the timequest timing analyzer, which completes the picture by providing the total solution for the highest reliable frequency of operation across process, voltage, and temp erature (pvt) variations. this chapter contains the following sections: ?memory interfaces pin support? on page 7?3 ?stratix iv external memory in terface features? on page 7?29 f for more information about external memo ry system performance specifications, board design guidelines, timing analysis, simulation, and debugging information, refer to the external memory interface handbook . february 2011 siv51007-3.2 7?2 chapter 7: external memory interfaces in stratix iv devices stratix iv device handbook february 2011 altera corporation volume 1 figure 7?1 shows an overview of the memory in terface data path that uses all the stratix iv i/o element (ioe) features. memory interfaces use stratix iv device feat ures such as delay-locked loops (dlls), dynamic oct control, read- and write-leveli ng circuitry, and i/o features such as oct, programmable input delay chains, pr ogrammable output delay, slew rate adjustment, and progra mmable drive strength. f for more information about i/o features, refer to the i/o features in stratix iv devices chapter. the altmemphy megafunction instantiates a phase-locked loop (pll) and pll reconfiguration logic to adjust the phase shift based on vt variation. vs f for more information about the stratix iv pll, refer to the clock networks and plls in stratix iv devices chapter. for more information about the altmemphy megafunction, refer to the external memory phy int erface (altmemphy) (nonafi) megafunction user guide . figure 7?1. external memory interface data path overview (1) , (2) notes to figure 7?1 : (1) you can bypass each register block. (2) the blocks used for each memory interface may differ sl ightly. the shaded blocks are part of the stratix iv ioe. (3) these signals may be bidirectio nal or unidirectional, depending on the memory standard. when bidirectio nal, the signal is ac tive during both read and write operations. ddr output and output enable registers memory stratix iv fpga dll ddr input registers alignment & synchronization registers half data rate output registers clock management & reset 4n 2n n n 2n 4n dpram (2) dq (read) (3) dq (write) (3) dqs logic block dqs (read) (3) half data rate input registers 2n half data rate output registers 42 dqs (write) (3) resynchronization clock alignment clock dqs write clock half-rate resynchronization clock half-rate clock alignment registers alignment registers 2n 2 dq write clock dqs enable circuit postamble control circuit postamble enable postamble clock ddr output and output enable registers chapter 7: external memory interfaces in stratix iv devices 7?3 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 memory interfaces pin support a typical memory interface requires data (d, q, or dq), data strobe (dqs/cq and dqsn/cqn), address, command, and clock pi ns. some memory interfaces use data mask (dm, bwsn, or nwsn) pins to enable write masking and qvld pins to indicate that the read data is ready to be capt ured. this section describes how stratix iv devices support all these different pins. 1 if you have more than one clock pair, you mu st place them in the same dq group. for example, if you have two clock pairs, you must place both of them in the same 4 dqs group. f for more information about pin connections, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . f for more information about pin planning and pin connections between a stratix iv device and an external memory device, refer to the external memory interface handbook . ddr3, ddr2, ddr sdram, and rldram ii devices use the ck and ck# signals to capture the address and command signals. generate these signals to mimic the write-data strobe using stratix iv ddr i/ o registers (ddios) to ensure that the timing relationships between the ck/ck# and dqs signals (t dqss , t dss , and t dsh in ddr3, ddr2, and ddr sdram devices or t ckdk in rldram ii devices) are met. qdr ii+ and qdr ii sram devices use the sa me clock (k/k#) to capture write data, address, and command signals. memory clock pins in stratix iv devices are generated using a ddio register going to differential output pins (refer to figure 7?2 ), marked in the pin table with diffout , diffio_tx , or diffio_rx prefixes. 7?4 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 f for more information about which pins to use for memory clock pins, refer to the external memory interface handbook . stratix iv devices offer differential input bu ffers for differential read-data strobe and clock operations. in addition, stratix iv devices also provide an independent dqs logic block for each cqn pin for comp lementary read-data strobe and clock operations. in the stratix iv pin tables, th e differential dqs pin pairs are denoted as dqs and dqsn pins, while the complement ary cq signals are denoted as cq and cqn pins. dqsn and cqn pins are marked se parately in the pin table. each cqn pin connects to a dqs logic block and the shif ted cqn signals go to the negative-edge input registers in the dq ioe registers. 1 use differential dqs signaling for ddr2 sdram interfaces running at or above 333 mhz. dq pins can be bidirectional signals, as in ddr3, ddr2, and ddr sdram, and rldram ii common i/o (cio) interfaces, or unidirectional signals, as in qdr ii+, qdr ii sram, and rldram ii separate i/o (sio) devices. connect the unidirectional read-data signals to stra tix iv dq pins and the unidirectional write-data signals to a different dqs/dq group than the read dqs/dq group. furthermore, the write clocks must be assi gned to the dqs/dqsn pins associated to this write dqs/dq group. do not use the cq/cqn pin-pair for write clocks. 1 using a dqs/dq group for the write-data signals minimizes output skew, allows access to the write-leveling circuitry (for ddr3 sdram interfaces), and allows vertical migration. these pi ns also have access to deskewing circuitry (using programmable delay chains) that can compen sate for delay mismatch between signals on the bus. figure 7?2. memory clock generation notes to figure 7?2 : (1) for pin location requirements,refer to the external memory interface handbook . (2) the mem_clk[0] and mem_clk_n[0] pins for ddr3, ddr2, and ddr sdram interfaces u se the i/o input buffer for feedback required by the altmemphy megafunction for tracking; th erefore, use bidirectional i/o buffers fo r these pins. for memory interfaces using a differential dqs input, the input feedback buffer is configured as differential input. for memory interfaces using a single-ended dqs input, the input buffer is configured as a single-ended in put. using a single-ended input feedback buffer requires that i/ o standard?s vref voltage is pro vided to that i/o bank?s vref pins. (3) to minimize jitter, regional clock networks are required for memory output clock generation. mem_clk (2) q d q d system clock (3) fpga les i/o elements v cc mem_clk_n (2 ) 1 0 chapter 7: external memory interfaces in stratix iv devices 7?5 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 the dqs and dq pin locations are fixed in th e pin table. memory interface circuitry is available in every stratix iv i/o bank that does not support transceivers. all the memory interface pins support the i/o st andards required to support ddr3, ddr2, ddr sdram, qdr ii+, qdr ii sram, and rldram ii devices. the stratix iv device family supports dqs and dq signals with dq bus modes of 4, 8/9, 16/18, or 32/36, although not all devices support dqs bus mode 32/36. when any of these pins are not used for memory interfacing, you can use them as user i/os. in addition, you can use any dqsn or cqn pins not used for clocking as dq (data) pins. table 7?1 lists pin support per dqs/dq bus mode, including the dqs/cq and dqsn/cqn pin pair. table 7?2 lists the number of dqs/dq groups available per side in each stratix iv device. for a more detailed listing of the number of dqs/dq groups available per bank in each stratix iv device, see figure 7?3 through figure 7?19 . these figures represent the die-top view of the stratix iv device. table 7?1. stratix iv dqs/dq bus mode pins mode dqsn support cqn support parity or dm (optional) qvld (optional) (1) typical number of data pins per group maximum number of data pins per group (2) 4 yes no no (6) no 4 5 8/9 (3) yes yes yes yes 8 or 9 11 16/18 (4) yes yes yes yes 16 or 18 23 32/36 (5) yes yes yes yes 32 or 36 47 32/36 (7) yes yes no (8) yes 32 or 36 39 notes to table 7?1 : (1) the qvld pin is not used in the altmemphy megafunction. (2) this represents the maximum number of dq pins (including parity, data mask, and qvld pins) connec ted to the dqs bus network with single-ended dqs signaling. when you use differential or compleme ntary dqs signaling, the maximum number of data per group decr eases by one. this number may vary per dqs/dq gr oup in a particular device. check the pin ta ble for the exact numbe r per group. for d dr3, ddr2, and ddr interfaces, the number of pins is fu rther reduced for an interfac e larger than 8 due to th e need of one dqs pin for ea ch 8/9 group that is used to form the x16/18 and 32/36 groups. (3) two 4 dqs/dq groups are stitched to make a 8/9 group so there are a total of 12 pins in this group. (4) four 4 dqs/dq groups are st itched to make a 16/18 group. (5) eight 4 dqs/dq groups are st itched to make a 32/3 6 group. (6) the dm pin can be supported if differential dqs is not used and the group does not have additional signals. (7) these 32/36 dqs/dq groups are available in ep4sgx290, ep4sgx360, and ep4sgx530 d evices in 1152- and 1517-pin fineline bga packages. there are 40 pins in each of these dqs/dq groups. (8) there are 40 pins in each of these dqs/dq groups. the bwsn pi ns cannot be placed within the sa me dqs/dq group as the write d ata pins because of insuffici ent pins available. table 7?2. number of dqs/dq groups in stratix iv devices per side (part 1 of 3) (1) device package side 4 (2) 8/9 16/18 32/36 (3) refer to: ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 780-pin fineline bga left 14 6 2 0 figure 7?3 top/bottom 17 8 2 0 right 0 0 0 0 ep4sgx290 ep4sgx360 780-pin fineline bga left/right 0 0 0 0 figure 7?5 top/bottom 18 8 2 0 7?6 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 ep4se230 ep4se360 780-pin fineline bga left/right 14 6 2 0 figure 7?4 top/bottom 17 8 2 0 ep4sgx110 1152-pin fineline bga (with 16 transceivers) right/left 7 3 1 0 figure 7?6 top/bottom 17 8 2 0 ep4sgx70 ep4sgx110 1152-pin fineline bga (with 24 transceivers) right/left 14 6 2 0 figure 7?7 top/bottom 17 8 2 0 ep4sgx180 ep4sgx230 1152-pin fineline bga right/left 13 6 2 0 figure 7?8 top/bottom 26 12 4 0 ep4sgx290 ep4sgx360 ep4sgx530 1152-pin fineline bga right/left 13 6 2 0 figure 7?9 top/bottom 26 12 4 2 (4) ep4se360 ep4se530 ep4se820 1152-pin fineline bga all sides 26 12 4 0 figure 7?10 ep4sgx180 ep4sgx230 1517-pin fineline bga all sides 26 12 4 0 figure 7?11 ep4sgx290 ep4sgx360 ep4sgx530 1517-pin fineline bga right/left 26 12 4 0 figure 7?12 top/bottom 26 12 4 2 (4) ep4se530 ep4se820 1517-pin fineline bga right/left 34 16 6 0 figure 7?13 top/bottom 38 18 8 4 ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g5 1517-pin fineline bga left 12 3 1 0 figure 7?14 top/bottom 26 12 4 0 right 11 4 1 0 ep4sgx290 ep4sgx360 ep4sgx530 1760-pin fineline bga right/left 26 12 4 0 figure 7?15 top/bottom 38 18 8 4 ep4se530 1760-pin fineline bga right/left 34 16 6 0 figure 7?16 top/bottom 38 18 8 4 ep4se820 1760-pin fineline bga right/left 40 18 6 0 figure 7?17 top/bottom 44 22 10 4 ep4sgx290 ep4sgx360 ep4sgx530 1932-pin fineline bga right/left 29 13 4 0 figure 7?18 top/bottom 38 18 8 4 table 7?2. number of dqs/dq groups in stratix iv devices per side (part 2 of 3) (1) device package side 4 (2) 8/9 16/18 32/36 (3) refer to: chapter 7: external memory interfaces in stratix iv devices 7?7 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 ep4s100g3 ep4s100g4 ep4s100g5 1932-pin fineline bga left 8 2 0 0 figure 7?19 top/bottom 38 18 8 4 right 7 1 0 0 notes to table 7?2 : (1) these numbers are preliminary until the devices are available. (2) some of the 4 groups may use r up and r dn pins. you cannot use these groups if you u se the stratix iv calibrated oct feature. (3) to interface with a 36 qdr ii+/qdr ii sram device in a stratix iv fpga that does no t support the 32/36 dqs/dq group, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (4) these 32/36 dqs/dq groups have 40 pins instead of 48 pins pe r group. bwsn pins cannot be placed within the same dqs/dq gro up as the write data pins because of insufficient pins available. table 7?2. number of dqs/dq groups in stratix iv devices per side (part 3 of 3) (1) device package side 4 (2) 8/9 16/18 32/36 (3) refer to: 7?8 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?3. number of dqs/dq groups per bank in ep4sgx 70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga package (1) , (2) , (3) , (4) . (5) notes to figure 7?3 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx70, ep4sgx110, ep4sgx180, and ep 4sgx230 devices do not support 32/36 mode . to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that incl ude that 4 group; however, there are rest rictions on using 8 /9 groups that in clude that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. (5) all i/o pin counts include dedicated clock inputs that you can use for data inputs. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 4a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 4c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 3c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 3a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 2a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 i/o bank 2c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 1c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 1a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?9 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?4. number of dqs/dq groups per bank in ep4se230 and ep4se360 devices in the 780-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?4 : (1) these numbers are preliminary until the devices are available. (2) ep4se230 and ep4se360 devices do not support 32/36 mode. to interface with a 36 qdr ii+ /qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that incl ude that 4 group; however, there are rest rictions on using 8 /9 groups that in clude that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. (5) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs. dll0 dll3 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 1a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 i/o bank 1c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 2c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 2a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 dll1 i/o bank 3a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 3c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 4c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 4a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 dll2 i/o bank 6a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 i/o bank 6c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 5c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 5a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 ep4se230 and ep4se360 devices in the 780-pin fineline bga 7?10 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?5. number of dqs/dq groups per bank in ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga package (1) , (2) notes to figure 7?5 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx290 and ep4sgx360 devices do no t support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8c i/o bank 7c i/o bank 7a i/o bank 4a i/o bank 4c i/o bank 3c i/o bank 3a 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?11 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?6. number of dqs/dq groups per bank in ep4sgx110 devices with 16 transceivers in the 1152-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?6 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx110 devices do not support 32/36 mode. to in terface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that incl ude that 4 group; however, there are rest rictions on using 8 /9 groups that in clude that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. (5) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs . dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 6a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 i/o bank 6c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 4a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 4c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 3c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 3a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 1c 26 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 1a 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 ep4sgx110 devices in the 1152-pin fineline bga (with 16 transceivers) 7?12 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?7. number of dqs/dq groups per bank in ep4sgx70 and ep4sgx110 devices with 24 transceivers in the 1152-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?7 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx70 and ep4sgx110 devices do not suppo rt 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that incl ude that 4 group; however, there are rest rictions on using 8 /9 groups that in clude that 4 group. (4) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs . (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 i/o bank 8a (3) 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 7a (3) 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 6a (3) 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 i/o bank 6c 26 user i/os (5) x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 1c (4) 26 user i/os (5) x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 1a (3) 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 ep4sgx70 and ep4sgx110 devices in the 1152-pin fineline bga (with 24 transceivers) dll1 dll2 i/o bank 4a (3) 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 4c 24 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 3c 24 user i/os x 4=2 x 8/ x 9=1 x 16/ x 18=0 i/o bank 3a (3) 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 6a (3) 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 i/o bank 6c 26 user i/os (5) x 4=3 x 8/ x 9=1 x 16/ x 18=0 i/o bank 1c (4) 26 user i/os (5) x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 chapter 7: external memory interfaces in stratix iv devices 7?13 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?8. number of dqs/dq groups per bank in ep4sgx180 and ep4sgx230 devices in the 1152-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?8 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx180 and ep4sgx230 devices do no t support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that incl ude that 4 group; however, there are rest rictions on using 8 /9 groups that in clude that 4 group. (4) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 1c i/o bank 1a 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 ep4sgx180 and ep4sgx230 devices in the 1152-pin fineline bga 7?14 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?9. number of dqs/dq groups per bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga package (1) , (3) , (4) , (5) notes to figure 7?9 : (1) these numbers are preliminary until the devices are available. (2) these 32/36 dqs/dq gr oups have 40 pins instead of 48 pins per group. (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that incl ude that 4 group; however, there are rest rictions on using 8 /9 groups that in clude that 4 group. (4) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x16/x18=1 x32/x36=1 (2) i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 1c i/o bank 1a 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x32/x36=1 (2) 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x32/x36=1 (2) 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x32/x36=1 (2) 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?15 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?10. number of dqs/dq groups per bank in ep4se360, ep4se530, and ep4se820 devices in the 1152-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?10 : (1) these numbers are preliminary until the devices are available. (2) ep4se360, ep4se5 30, and ep4se820 devices do not supp ort 32/36 mode. to in terface with a 36 qdr ii+/qdr ii sram device, refe r to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. (5) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 ep4se360, ep4se530 and ep4se820 devices in the 1152-pin fineline bga 7?16 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?11. number of dqs/dq groups per bank in ep4s gx180 and ep4sgx230 devices in the 1517-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?11 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx180 and ep4sgx230 devices do no t support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 ep4sgx180 and ep4sgx230 devices in the 1517-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?17 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?12. number of dqs/dq groups per bank in ep4s gx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga package (1) , (3) , (4) , (5) notes to figure 7?12 : (1) these numbers are preliminary until the devices are available. (2) these 32/36 dqs/dq gr oups have 40 pins instead of 48 pins per group. (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=1 (2) i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=1 (2) 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=1 (2) 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=1 (2) 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 48 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga 7?18 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?13. number of dqs/dq groups per bank in ep4se530 and ep4se820 devices in the 1517-pin fineline bga package (1) , (2) , (3) , (4) notes to figure 7?13 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated co rner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6b i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1b i/o bank 1a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5b 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2b 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 ep4se530 and ep4se820 devices in the 1517-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?19 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?14. number of dqs/dq groups per bank in ep 4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga package (1) , (2) , (3) , (4) , (5) notes to figure 7?14 : (1) these numbers are preliminary until the devices are available. (2) ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices do not support ? 32/ ? 36 mode. to interface with a ? 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?26 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (4) all i/o pin counts include dedicated cloc k inputs that you can use for data inputs. (5) you can also use some of the dq s/dq pins in i/o bank 1c as configuration pins. you cannot use a ? 4 dqs/dq group with any of its pin members used for configuration purposes. make sure that the dqs/dq groups that you have cho sen are not used for configuration as you ma y lose up to four ? 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 i/o bank 8a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 44 user i/os x 4=5 x 8/ x 9=1 x 16/ x 18=0 21 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 21 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 46 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 dll1 dll2 i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 40 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 43 user i/os x 4=5 x 8/ x 9=1 x 16/ x 18=0 20 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 21 user i/os x 4=1 x 8/ x 9=0 x 16/ x 18=0 46 user i/os x 4=6 x 8/ x 9=2 x 16/ x 18=1 ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga 7?20 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?15. number of dqs/dq groups per bank in ep4s gx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga package (1) , (2) , (3) , (4) notes to figure 7?15 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (3) all i/o pin counts include dedicated cl ock inputs and dedicated corn er pll clock inputs that yo u can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16// x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 6/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?21 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?16. number of dqs/dq groups per bank in ep4se530 devices in the 1760-pin fineline bga package (1) , (2) , (3) , (4) notes to figure 7?16 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (3) all i/o pin counts include dedicated cl ock inputs and dedicated corn er pll clock inputs that yo u can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6b i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1b i/o bank 1a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5b 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2b 24 user i/os x 4=4 x 8/ x 9=2 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 ep4se530 devices in the 1760-pin fineline bga 7?22 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 figure 7?17. number of dqs/dq groups per bank in ep4se820 devices in the 1760-pin fineline bga package (1) , (2) , (3) , (4) notes to figure 7?17 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated co rner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6b i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1b i/o bank 1a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 36 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 36 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5b 36 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2b 36 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 ep4se820 devices in the 1760-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?23 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 figure 7?18. number of dqs/dq groups per bank in ep4s gx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga package (1) , (2) , (3) , (4) notes to figure 7?18 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated co rner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 42 user i/os x 4=6 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 5b 20 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 i/o bank 5a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 i/o bank 2b 20 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 i/o bank 2a 50 user i/os x 4=7 x 8/ x 9=3 x 16/ x 18=1 x 32/ x 36=0 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga 7?24 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 the dqs and dqsn pins are listed in the stratix iv pin tables as dqsxy and dqsnxy , respectively, where x indicates the dqs/dq grouping number and y indicates whether the group is located on the top (t), bott om (b), left (l), or right (r) side of the device. the dqs/dq pin numbering is based on 4 mode. the corresponding dq pins are marked as dqxy , where x indicates which dqs group the pins belong to and y indicates whether the group is located on the top (t), bottom (b), left (l), or right (r) side of the device. for example, dqs1l indicates a dqs pin located on the left side of the device. the dq pins belonging to that group are shown as dq1l in the pin table. for more information, refer to figure 7?20 . figure 7?19. number of dqs/dq groups per bank in ep 4s100g3, ep4s100g4, and ep4s100g5 devices in the 1932-pin fineline bga package (1) , (2) , (3) , (4) notes to figure 7?19 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/ 36 groups that include th at 4 group, however there are restrict ions on using 8/9 groups that inc lude that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated co rner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chos en are not also used fo r configuration because you may lose up to four 4 dqs/dq groups, depend ing on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1a 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 38 user i/os x 4=3 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 20 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 17 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 32 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 48 user i/os x 4=8 x 8/ x 9=4 x 16/ x 18=2 x 32/ x 36=1 40 user i/os x 4=3 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 19 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 19 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 i/o bank 5b 12 user i/os x 4=0 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 i/o bank 5a 40 user i/os x 4=4 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 i/o bank 2b 13 user i/os x 4=1 x 8/ x 9=0 x 16/ x 18=0 x 32/ x 36=0 i/o bank 2a 39 user i/os x 4=4 x 8/ x 9=1 x 16/ x 18=0 x 32/ x 36=0 ep4s100g3, ep4s100g4, and ep4s100g5 devices in the 1932-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?25 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 1 the parity, dm, bwsn, nwsn, ecc, and qvld pins are shown as dq pins in the pin table. the numbering scheme starts from the top-left corner of the device going counter-clockwise in a die-top view. figure 7?20 shows how the dqs/dq groups are numbered in a die-top view of the device. the top and bottom sides of the device can contain up to 38 4 dqs/dq groups. the left and right sides of the device can contain up to 34 4 dqs/dq groups. figure 7?20. dqs pins in stratix iv i/o banks 8a 8b 8c 7c 7b 7a dqs38t dqs1l 1a 1b 1c 2c 2b 2a dqs34l 3a 3b 3c 4c 4b 4a 5a 5b 5c 6c 6b 6a dqs17l dqs20t dqs19t dqs1t dqs34r dqs18r dqs1r dqs1b dqs19b dqs20b dqs38b dqs17r dqs18l stratix iv device pll_l1 dll0 pll_l4 dll1 pll_r4 dll2 dll3 pll_r1 pll_l2 pll_l3 pll_r2 pll_r3 pll_t1 pll_t2 pll_b2 pll_b1 7?26 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 using the r up and r dn pins in a dqs/dq group used for memory interfaces you can use the dqs/dqsn pins in some of the 4 groups as r up and r dn pins (listed in the pin table). you cannot use a 4 dqs/dq group for memory interfaces if any of its pin members are used as r up and r dn pins for oct calibration. you may be able to use the 8/9 group that includes this 4 dqs/dq group, if either of the following applies: you are not using dm pins with your differential dqs pins you are not using complementary or differential dqs pins you can use the 8/9 group because a dq s/dq 8/9 group actually comprises 12 pins, as the groups are formed by stitching two dqs/dq groups in 4 mode with six pins each (refer to table 7?1 on page 7?5 ). a typical 8 memory interface consists of one dqs, one dm, and eight dq pins that add up to 10 pins. if you choose your pin assignment carefully, you can use the two extra pins for r up and r dn . in a ddr3 sdram interface, you must use differential dqs, which means that you only have one extra pin. in this case, pick different pin locations for the r up and r dn pins (for example, in the bank that contains the address and command pins). you cannot use the r up and r dn pins shared with dqs/dq group pins when using 9 qdr ii+/qdr ii sram devices, as the r up and r dn pins are dual purpose with the cqn pins. in this case, pick different pin locations for r up and r dn pins to avoid conflict with memory interfac e pin placement. in this case, you have the choice of placing the r up and r dn pins in the data-write group or in the same bank as the address and command pins. there is no restriction on using 16/18 or 32/36 dqs/dq groups that include the 4 groups whose pins are being used as r up and r dn pins, because there are enough extra pins that can be used as dqs pins. 1 for 8, 16/18, or 32/36 dqs/dq groups whose members are used for r up and r dn , you must assign dqs and dq pins manually. the quartus ? ii software might not be able to place dqs and dq pins with out manual pin assignments, resulting in a ?no-fit?. combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface this implementation combines 16/18 dqs/dq groups to interface with a 36 qdr ii+/qdr ii sram device. the 36 read data bus uses two 16/18 groups while the 36 write data uses another two 16/18 or four 8/9 groups. the cq/cqn signal traces are split on the boar d trace to connect to two pairs of cq/cqn pins in the fpga. this is the only connection on the board that you need to change for this implementation. other qdr ii+/qdr ii sram interface rules for stratix iv devices also apply for this implementation. 1 the altmemphy megafunction and uniphy-based external memory interface ips do not use the qvld signal, so you can leave the qvld signal unconnected as in any qdr ii+/qdr ii sram interface. f for more information about the altmemph y megafunction or uniphy-based ips, refer to the external memory interface handbook . chapter 7: external memory interfaces in stratix iv devices 7?27 memory interfaces pin support february 2011 altera corporation stratix iv device handbook volume 1 rules to combine groups in 780-, 1152-, and some 1517-pin package devi ces, there is at most one 16/18 group per i/o sub-bank. you can combine two 16 /18 groups from a single side of the device for a 36 interface. for devices that do not have four 16/18 groups in a single side of the device to form two 36 groups for read and write data , you can form one 36 group on one side of the device and another 36 group on the other side of the device. for vertical migration with the 36 emulation implementation, check if migration is possible by enabling device migration in the quartus ii project. the quartus ii software supports the use of four 8/9 dq groups for write data pins and migration of these groups across device density. table 7?3 lists the possible combinations to use two 16/18 dqs/dq groups to form a 32/ 36 group on stratix iv devices lacking a native 32/36 dqs/dq group. table 7?3. possible group combinations in stratix iv devices (part 1 of 2) package device density i/o sub-bank combinations 780-pin fineline bga ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 3a and 4a, 7a and 8a (bottom and top i/o banks) (1) ep4se230 ep4se360 1a and 2a, 5a and 6a (left and right i/o banks) 3a and 4a, 7a and 8a (bottom and top i/o banks) (1) 1152-pin fineline bga ep4sgx70 ep4sgx110 3a and 4a, 7a and 8a (bottom and top i/o banks) (1) ep4sgx180 ep4sgx230 ep4sgx290 (2) ep4sgx360 (2) ep4sgx530 (2) 1a and 1c, 6a and 6c (left and right i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 7a and 7b, 8a and 8b (top i/o banks) ep4se360 ep4se530 ep4se820 1a and 1c, 2a and 2c (left i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 5a and 5c, 6a and 6c (right i/o banks) 7a and 7b, 8a and 8b (top i/o banks) 7?28 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook february 2011 altera corporation volume 1 1517-pin fineline bga ep4sgx180 ep4sgx230 ep4sgx290 (2) ep4sgx360 (2) ep4sgx530 (2) 1a and 1c, 2a and 2c (left i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 5a and 5c, 6a and 6c (right i/o banks) 7a and 7b, 8a and 8b (top i/o banks) ep4se530 (2) ep4se820 (2) 1a and 1b, 2a and 2b or 1b and 1c, 2b and 2c (left i/o banks) (3) 5a and 5b, 6a and 6b or 5b and 5c, 6b and 6c (right i/o banks) (3) ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g5 3a and 3b, 4a and 4b (bottom i/o banks) 7a and 7b, 8a and 8b (top i/o banks) 1760-pin fineline bga ep4sgx290 ep4sgx360 ep4sgx530 1a and 1c, 2a and 2c (left i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 5a and 5c, 6a and 6c (right i/o banks) 7a and 7b, 8a and 8b (top i/o banks) ep4se530 (2) ep4se820 (2) 1a and 1b, 2a and 2b or 1b and 1c, 2b and 2c (left i/o banks) (3) 5a and 5b, 6a and 6b or 5b and 5c, 6b and 6c (right i/o banks) (3) 1932-pin fineline bga ep4sgx290 (2) ep4sgx360 (2) ep4sgx530 (2) 1a and 1c, 2a and 2c (left i/o banks) 5a and 5c, 6a and 6c (right i/o banks) notes to table 7?3 : (1) each side of the device in these packages has four remaining 8/9 gr oups. you can combine them for the write side (only) if you want to keep the 36 qdr ii+/qdr ii sram interface on one si de of the device. you must change the memory interfac e data group default assignment from the default 18 to 9 in this case. (2) this device supports 36 dqs/dq groups on the top and bottom i/o banks natively. (3) although it is possible to combine the 16/18 dqs/dq groups from i/o banks 1a and 1c, 2a and 2c, 5a and 5c, and 6a and 6c, altera does not recommend this due to the size of the package. similarly, crossing a bank number (for example, combining groups from i/o banks 6c and 5c) is not supported in this package. table 7?3. possible group combinations in stratix iv devices (part 2 of 2) package device density i/o sub-bank combinations chapter 7: external memory interfaces in stratix iv devices 7?29 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 stratix iv external memory interface features stratix iv devices are rich with features th at allow robust high-performance external memory interfacing. the altmemphy megafunction allows you to use these external memory interface features and help s set up the physical interface (phy) best suited for your system. this section describes each stratix iv device feature that is used in external memory interfaces from the dqs phase-shift circuitry, dqs logic block, leveling multiplexers, and dynamic oct control block. 1 the altmemphy megafunction and the altera memory controller megacore ? functions can run at half the frequency of the i/o interface of the memory devices to allow better timing management in high-sp eed memory interfaces. stratix iv devices have built-in registers in the ioe to convert data from full-rate (the i/o frequency) to half-rate (the controller freq uency) and vice versa. you can bypass these registers if your memory controller is not running at half the rate of the i/o frequency. when using the altera memory controller megacore functions, the altmemphy megafunction is instantiated for you. f for more information about the altmemphy megafunction, refer to the external memory phy interface (altmemphy) (nonafi) megafunction user guide . dqs phase-shift circuitry stratix iv phase-shift circuitry provides ph ase shift to the dqs/cq and cqn pins on read transactions when the dqs/cq and cqn pins are acting as input clocks or strobes to the fpga. the dqs phase-shift circ uitry consists of dlls that are shared between multiple dqs pins and the phase-of fset module to further fine-tune the dqs phase shift for different sides of the device. 7?30 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 figure 7?21 shows how the dqs phase-shift circ uitry is connected to the dqs/cq and cqn pins in the device where memory interfaces are supported on all sides of the stratix iv device. dqs phase-shift circuitry is connected to the dqs logic blocks that control each dqs/cq or cqn pin. the dqs logic blocks allow the dqs delay settings to be updated concurrently at every dqs/cq or cqn pin. figure 7?21. dqs/cq and cqn pins and dqs phase-shift circuitry (1) , (2) notes to figure 7?21 : (1) for possible refere nce input clock pins fo r each dll, refer to ?dll? on page 7?31 . (2) you can configure each dqs/cq and cqn pin with a phase shift based on one of two possible dll output settings. dll reference clock dqs phase-shift circ u itry dqs/cq pin cqn pin cqn pin dqs/cq pin to ioe t t t t dqs phase-shift circ u itry dll reference clock dll reference clock dqs/cq pin cqn pin dqs/cq pin cqn pin to ioe to ioe to ioe t t t to ioe t dq s logic block s dqs/cq pin cqn pin cqn pin dqs/cq pin to ioe to ioe to ioe to ioe t t t t dqs/cq pin cqn pin dqs/cq pin cqn pin t t t t dqs logic blocks dll reference clock dqs phase-shift circ u itry to ioe to ioe to ioe dqs phase-shift circ u itry to ioe to ioe to ioe to ioe chapter 7: external memory interfaces in stratix iv devices 7?31 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 dll dqs phase-shift circuitry uses a dll to dynamically control the clock delay needed by the dqs/cq and cqn pin. the dll, in turn, uses a frequency reference to dynamically generate control signals for the delay chains in each of the dqs/cq and cqn pins, allowing it to compensate for pvt variations. the dqs delay settings are gray-coded to reduce jitter when the d ll updates the settings. the phase-shift circuitry needs 1,280 clock cycl es to lock and calculate the correct input clock period when the dll is in low jitter mode. otherw ise, only 256 clock cycles are needed. do not send data during these clock cycles beca use there is no guarantee that it will be captured properly. as the settings from th e dll may not be stable until this lock period has elapsed, be aware that anythi ng using these settings (including the leveling delay system) may be unstable during this period. 1 you can still use the dqs phase- shift circuitry for any memory interfaces that are less than 100 mhz. however, the dqs signal may not shift over 2.5 ns. even if the dqs signal is not shifted exactly to the middle of the dq valid window, the i/o element should still be able to capture the data in low-frequency applications in which a large amount of timing margin is available. there are a maximum of four dlls in a stratix iv device, located in each corner of the device. these four dlls support a maximum of four unique frequencies, with each dll running at one frequency. each dll ca n have two outputs with different phase offsets, which allows one stratix iv device to have eight different dll phase shift settings. 7?32 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 figure 7?22 shows the dll and i/o bank locations in stratix iv devices from a die-top view if all sides of the device support external memory interfaces. the dll can access the two adjacent sides fr om its location within the device. for example, dll0 on the top left of the device can access the top side (i/o banks 7a, 7b, 7c, 8a, 8b, and 8c) and the left side of th e device (i/o banks 1a, 1b, 1c, 2a, 2b, and 2c). this means that each i/o bank is acce ssible by two dlls, giving more flexibility to create multiple frequencies and mult iple-type interfaces. you can have two different interfaces with the same frequency on the two sides adjacent to a dll, where the dll controls the dqs delay settings for both interfaces. each bank can use settings from either or both dlls the bank is adjacent to. for example, dqs1l can get its phase-shift settings from dll0, while dqs2l can get its phase-shift settings from dll1. table 7?4 lists the dll location and supported i/o banks for stratix iv devices. figure 7?22. stratix iv dll and i/o bank locations (die-top view) pll_t1 pll_t2 pll_b1 pll_b2 stratix iv fpga 8a 8b 8c 7c 7b 7a 3a 3b 3c 4c 4b 4a 2a 2b 2c pll_l2 1c 1b 1a 5a 5b 5c 6c 6b 6a 6 6 6 6 6 6 6 6 dll0 pll_l1 dll3 pll_r1 dll2 pll_r4 dll1 pll_l4 pll_r3 pll_r2 pll_l3 chapter 7: external memory interfaces in stratix iv devices 7?33 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 1 you can only have one memory interface in each i/o sub-bank (such as i/o sub-banks 1a, 1b, and 1c) when you use leveling delay chains. this is because there is only one leveling delay chain per i/o sub-bank. the reference clock for each dll may come from pll output clocks or any of the two dedicated clock input pins located in either side of the dll. table 7?5 through table 7?17 lists the available dll reference clock input resources for the stratix iv device family. 1 when you have a dedicated pll that only ge nerates the dll input reference clock, set the pll mode to no compensation to achieve better performance or the quartus ii software changes it automatically. because the pll does not use any other outputs, it does not need to compensate for any clock paths. table 7?4. dll location and supported i/o banks dll location accessible i/o banks (1) dll0 top-left corner 1a, 1b, 1c, 2a, 2b, 2c, 7a, 7b, 7c, 8a, 8b, 8c dll1 bottom-left corner 1a, 1b, 1c, 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b, 4c dll2 bottom-right corner 3a, 3b, 3c, 4a, 4b, 4c, 5a, 5b, 5c, 6a, 6b, 6c dll3 top-right corner 5a, 5b, 5c, 6a, 6b, 6c, 7a, 7b, 7c, 8a, 8b, 8c note to table 7?4 : (1) the dll can access these i/o banks if th ey are available for memory interfacing. table 7?5. dll reference clock input for ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p ? pll_b1 ? ? dll3 clk12p clk13p clk14p clk15p ? pll_t1 ? ? 7?34 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 table 7?6. dll reference clock input for ep4se230 and ep4se360 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l2 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b1 pll_r2 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t1 pll_r2 ? table 7?7. dll reference clock input for ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p ? pll_t1 ? ? dll1 clk4p clk5p clk6p clk7p ? pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p ? pll_b2 ? ? dll3 clk12p clk13p clk14p clk15p ? pll_t2 ? ? chapter 7: external memory interfaces in stratix iv devices 7?35 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 table 7?8. dll reference clock input for ep4sgx70 and ep4sgx110 devices in the 1152-pin fineline bga package (with 24 transceivers) dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l2 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b1 pll_r2 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t1 pll_r2 ? table 7?9. dll reference clock input for ep4sgx110 devices in the 1152-pin fineline bga package (with 16 transceivers) dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p clk10p clk11p pll_b1 ? ? dll3 clk12p clk13p clk14p clk15p clk10p clk11p pll_t1 pll_r2 ? 7?36 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 table 7?10. dll reference clock input for ep4sgx180, ep4s gx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p clk10p clk11p pll_b2 ? ? dll3 clk12p clk13p clk14p clk15p clk10p clk11p pll_t2 pll_r2 ? table 7?11. dll reference clock input for ep4se360, ep4se530, and ep4se820 devices in the 1152-pin fineline bga packages dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 ? chapter 7: external memory interfaces in stratix iv devices 7?37 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 table 7?12. dll reference clock input for ep4se530 and ep4se820 devices in the 1517- and 1760-pin fineline bga packages dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 pll_l1 dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 pll_l4 dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 pll_r4 dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 pll_r1 table 7?13. dll reference clock input for ep4sgx180, ep4s gx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 ? 7?38 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 table 7?14. dll reference clock input for ep4s40g2, ep4s40g 5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk1p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk1p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk10p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk10p pll_t2 pll_r2 ? table 7?15. dll reference clock input for ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 ? chapter 7: external memory interfaces in stratix iv devices 7?39 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 table 7?16. dll reference clock input for ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 pll_l1 dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 pll_l4 dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 pll_r4 dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 pll_r1 table 7?17. dll reference clock input for ep4s100g3, ep4s100g 4, and ep4s100g5 devices in the 1932-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p ? pll_t1 pll_l2 pll_l1 dll1 clk4p clk5p clk6p clk7p ? pll_b1 pll_l3 pll_l4 dll2 clk4p clk5p clk6p clk7p clk9p clk11p pll_b2 pll_r3 pll_r4 dll3 clk12p clk13p clk14p clk15p clk9p clk11p pll_t2 pll_r2 pll_r1 7?40 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 figure 7?23 shows a simple block diagram of the dll. the input reference clock goes into the dll to a chain of up to 16 delay elements. the phase comparator compares the signal coming out of the end of the dela y chain block to the input reference clock. the phase comparator then issues the upndn signal to the gray -code counter. this signal increments or decrements a six-bi t delay setting (dqs delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming ou t of the delay element chain in phase. 1 in the quartus ii assignment, phase offset control block ?a? is designated as dlloffsetctrl_ chapter 7: external memory interfaces in stratix iv devices 7?41 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 there are eight different frequency modes for the stratix iv dll, as listed in table 7?18 . each frequency mode provides different phase shift selections. in frequency mode 0, 1, 2, and 3, the 6-bit dqs delay settings vary with pvt to implement the phase-shift delay. in frequency modes 4, 5, 6, and 7, only 5 bits of the dqs delay settings vary with pvt to impl ement the phase-shift delay; the most significant bit of the dqs delay setting is set to 0. f for the frequency range of each mode, refer to the dc and switching characteristics for stratix iv devices chapter. for 0 shift, the dqs/cq signal bypasse s both the dll and dqs logic blocks. the quartus ii software automatically sets the dq input delay chains so that the skew between the dq and dqs/cq pin at the dq ioe registers is negligible when 0 shift is implemented. you can feed the dqs delay settings to the dqs logic block and logic array. the shifted dqs/cq signal goes to the dqs bus to clock the ioe input registers of the dq pins. the signal can also go into the logic array for resynchronization if you are not using ioe resynchronization registers. th e shifted cqn signal can only go to the negative-edge input register in the dq ioe and is only used for qdr ii+ and qdr ii sram interfaces. phase offset control each dll has two phase-offset modules and can provide two separate dqs delay settings with independent offsets, one for the top and bottom i/o bank and one for the left and right i/o bank, so you can fine -tune the dqs phase-shift settings between two different sides of the device. even though you have independent phase offset control, the frequency of the interface using the same dll must be the same. use the phase offset control module for making small shifts to the input signal and use the dqs phase-shift circuitry for larger signal shifts. for example, if the dll only offers a multiple of 30 phase shift, but your inte rface needs a 67.5 ph ase shift on the dqs signal, you can use two delay chains in the dqs logic blocks to give you 60 phase shift and use the phase offset control feature to implement the extra 7.5 phase shift. table 7?18. stratix iv dll frequency modes frequency mode available phase shift number of delay chains 0 22.5, 45, 67.5, 90 16 1 30, 60, 90, 120 12 2 36, 72, 108, 144 10 3 45, 90, 135, 180 8 4 30, 60, 90, 120 12 5 36, 72, 108, 144 10 6 45, 90, 135, 180 8 7 60, 120, 180, 240 6 7?42 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 you can use either a static phase offset or a dynamic phase offset to implement the additional phase shift. the available additi onal phase shift is implemented in 2?s: complement in gray-code between settings ?64 to +63 for frequency mode 0, 1, 2, and 3, and between settings ?32 to +31 for frequenc y modes 4, 5, 6, and 7. an additional bit indicates whether the setting has a positive or negative value. the settings are linear, each phase offset setting adds a delay amount specified in the dc and switching characteristics for stratix iv devices chapter. the dqs phase shift is the sum of the dll delay settings and the user-selected phase offset settings whose top setting is 64 for frequency modes 0, 1, 2, and 3; and 32 for frequency modes 4, 5, 6, and 7, so the actual physical offset setting range is 64 or 32 su btracted by the dqs delay settings from the dll. 1 when using this feature, you need to mo nitor the dqs delay settings to know how many offsets you can add and subtract in th e system. note that the dqs delay settings output by the dll are also gray coded. for example, if the dll determines that dqs delay settings of 28 is needed to achieve a 30 phase shift in dll frequency mode 1, you can subtract up to 28 phase offset settings and you can add up to 35 phase of fset settings to achieve the optimal delay that you need. however, if the same dqs delay settings of 28 is needed to achieve 30 phase shift in dll frequency mode 4, you can still subtract up to 28 phase offset settings, but you can only add up to 3 ph ase offset settings before the dqs delay settings reach their maximum settings because dll frequency mode 4 only uses 5-bit dll delay settings. f for more information about the value for each step, refer to the dc and switching characteristics for stratix iv devices chapter. when using static phase offset, you can specify the phase offset amount in the altmemphy megafunction as a positive numb er for addition or a negative number for subtraction. you can also have a dynami c phase offset that is always added to, subtracted from, or both added to and subtracted from the dll phase shift. when you always add or subtract, you can dynamically input the phase offset amount into the dll_offset[5..0] port. when you want to both add and subtract dynamically, you control the addnsub signal in addition to the dll_offset[5..0] signals. 7?43 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 dqs logic block each dqs/cq and cqn pin is connected to a separate dqs logic block, which consists of the dqs delay chains, update enable circuitry, and dqs postambl e circuitry, as shown in figure 7?24 . figure 7?24. stratix iv dqs logic block notes to figure 7?24 : (1) the input reference clock for the dqs phas e-shift circuitry can come from a pll outp ut clock or an inpu t clock pin. for more information, refer to table 7?5 on page 7?33 through table 7?17 on page 7?39 . (2) the dqsenable signal can also come from the stratix iv fpga fabric. d d update ena b le circ u itry 6 6 6 6 4 6 6 6 dqs delay settings from the dqs phase-shift circ u itry dqs/cq or cqn pin d q sin delayctrlin [5:0] offsetctrlin [5:0] 7?44 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 dqs delay chain dqs delay chains consist of a set of variable delay elements to allow the input dqs/cq and cqn signals to be shifted by the amount specified by the dqs phase-shift circuitry or the logic array. there are four delay elements in the dqs delay chain; the first delay chain closest to the dqs/cq pin can be shifted either by the dqs delay settings or by the sum of the dqs delay setting and the phase-offset setting. the number of delay chains required is transparent because the altmemphy megafunction automatically sets it when you choose the operating frequency. the dqs delay settings can come from the dqs phase-shift circuitry on either end of the i/o banks or from the logic array. the delay elements in the dqs logic block have the same characteristics as the delay elements in the dll. when the dll is not used to control the dqs delay chains, you can input your own gray-coded 6-bit or 5-bit settings using the dqs_delayctrlin[5..0] signals available in the al tmemphy megafunction. these settings control 1, 2, 3, or all 4 delay elements in the dqs delay chains. the altmemphy megafunction ca n also dynamically choose the number of dqs delay chains needed for the system. the amount of delay is equal to the sum of the delay element?s intrinsic delay and the product of the number of delay steps and the value of the delay steps. you can also bypass the dqs delay ch ain to achieve a 0 phase shift. update enable circuitry both the dqs delay settings and the phase-offset settings pass through a register before going into the dqs delay chains. the registers are controlled by the update enable circuitry to allow enough time for an y changes in the dqs delay setting bits to arrive at all the delay elements. this allows them to be adjusted at the same time. the update enable circuitry enables the registers to allow enough time for the dqs delay settings to travel from the dqs phase-shift circuitry or core logic to all the dqs logic blocks before the next change. it uses the in put reference clock or a user clock from the core to generate the update enable output. the altmemphy megafunction uses this circuit by default. figure 7?25 shows an example waveform of the update enable circuitry output. figure 7?25. dqs update enable waveform update enable circuitry output system clock dqs delay settings (updated every 8 cycles) dll counter update (every 8 cycles) 6 bit dll counter update (every 8 cycles) chapter 7: external memory interfaces in stratix iv devices 7?45 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 dqs postamble circuitry for external memory interfaces that use a bi directional read strobe such as in ddr3, ddr2, and ddr sdram, the dqs signal is low before going to or coming from a high-impedance state. the state in which dqs is low, just after a high-impedance state, is called the preamble; the state in wh ich dqs is low, just before it returns to a high-impedance state, is called the postamble. there are preamble and postamble specifications for both read and write op erations in ddr3, ddr2, and ddr sdram. the dqs postamble circuitry ensures that data is not lost if there is noise on the dqs line during the end of a read operation that occurs while dqs is in a postamble state. stratix iv devices have dedicated postamble registers that you can control to ground the shifted dqs signal used to clock the dq input registers at the end of a read operation. this ensures that any glitches on the dqs input signals during the end of a read operation that occurs while dqs is in a postamble state do not affect the dq ioe registers. in addition to the dedicated postamble regis ter, stratix iv devices also have an hdr block inside the postamble enable circuitry. use these registers if the controller is running at half the frequency of the i/os. using the hdr block as the first stage capture register in the postamble enable circuitry block is optional. the hdr block is clocked by the half-rate resynchronization clock, which is the output of the i/o clock divider circuit (shown in figure 7?31 on page 7?49 ). there is an and gate after the postamble register outputs that is used to avoid postamble glitch es from a previous read burst on a non-consecutive read burst. this scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency for dqsenable de-assertion, as shown in figure 7?26 . figure 7?26. avoiding glitch on a non-consecutive read burst waveform delayed by 1/2t logic preamble postamble postamble glitch dqs postamble enable dqsenable 7?46 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 leveling circuitry ddr3 sdram unbuffered modules use a fly-by clock distribution topology for better signal integrity. this means that the ck /ck# signals arrive at each ddr3 sdram device in the module at different times. the difference in arrival time between the first ddr3 sdram device and the last device on the module can be as long as 1.6 ns. figure 7?27 shows the clock topology in ddr3 sdram unbuffered modules. because the data and read strobe signals are still point-to-point, take special care to ensure that the timing relationship between the ck/ck# and dqs signals ( tdqss , tdss , and tdsh ) during a write is met at every de vice on the modules. furthermore, read data coming back into the fpga from the memory is also st aggered in a similar way. stratix iv fpgas have leveling circuitry to address these two situations. there is one leveling circuitry per i/o sub-bank (for ex ample, i/o sub-bank 1a, 1b, and 1c each has one leveling circuitry). these delay ch ains are pvt-compensated by the same dqs delay settings as the dll and dqs delay chains. for frequencies equal to and above 400 mhz, the dll uses eight delay chains, such that each delay chain generates a 45 delay. the generated clock phases are distributed to every dqs logic block that is available in the i/o sub-bank. the delay chain taps then feeds a multiplexer contro lled by the altmemphy megafunction to select which clock phases are to be used for that 4 or 8 dqs group. each group can use a different tap output from the read-lev eling and write-leveling delay chains to compensate for the different ck/ck# delay going into each device on the module. figure 7?27. ddr3 sdram unbuffered module clock topology dqs/dq dqs/dq dqs/dq dqs/dq dqs/dq dqs/dq ck/ck# stratix iv device dqs/dq dqs/dq chapter 7: external memory interfaces in stratix iv devices 7?47 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 figure 7?28 and figure 7?29 show the stratix iv write- and read-leveling circuitry. the ?90 write clock of the altmemphy megafunction feeds the write-leveling circuitry to produce the clock to gene rate the dqs and dq signals. during initialization, the altmemphy megafunction picks the correct write-leveled clock for the dqs and dq clocks for each dqs/dq group after sweeping all the available clocks in the write calibration process. th e dq clock output is ?90 phase-shifted compared to the dqs clock output. similarly, the resynchronization clock feeds the read-leveling circuitry to produce the optimal resynchronization and postamble clock for each dqs/dq group in the calibration process. the resynchronizatio n and postamble clocks can use different clock outputs from the leveling circuitry. the output from the read-leveling circuitry can also generate the half-rate resynchroni zation clock that goes to the fpga fabric. figure 7?28. stratix iv write-leveling delay chains and multiplexers (1) note to figure 7?28 : (1) there is one leveling delay chain per i/o sub-bank (for example, i/o sub-banks 1a, 1b, and 1c). you can only have one memory interface in each i/o sub-bank when you use the l eveling delay chain. write clk (-90 0 ) write-leveled dqs clock write-leveled dq clock figure 7?29. stratix iv read-leveling delay chains and multiplexers (1) notes to figure 7?29 : (1) there is one leveling delay ch ain per i/o sub-bank (for example, i/o sub-ba nks 1a, 1b, and 1c). you can only have one memory interface in each i/o sub-bank when you u se the leveling delay chain. (2) each divider feeds up to six pins (from a ? 4 dqs group) in the device. to feed wider dqs groups, you must chain multiple clock dividers together by feeding the slaveout output of one divider to the masterin input of the neighboring pins? divider. dqs half-rate resynchronization clock read-leveled resynchronization clock half-rate source synchronous clock resynchronization clock (resync_clk_2x) 6 phasectrlin phaseinvertctrl delayctrlin 0111 0110 0100 0011 0010 0001 0000 0101 0 1 4 dff 0 1 0 1 slaveout masterin i/o clock divider (2) use_masterin phaseselect clkout 7?48 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 1 the altmemphy megafunction dynamically calibrates the alignment for read- and write-leveling during the initialization process. f for more information about the altmemphy megafunction, refer to the external memory phy interface (altmemphy) (nonafi) megafunction user guide . dynamic on-chip termination control figure 7?30 shows the dynamic oct control block. the block includes all the registers needed to dynamically turn on oct rt duri ng a read and turn oct rt off during a write. f for more information about dynamic on-c hip termination control, refer to the i/o features in stratix iv devices chapter. figure 7?30. stratix iv dynamic oct control block note to figure 7?30 : (1) the write clock comes from either th e pll or the write-leveling delay chain. oct control write clock (1) oct enable resynchronization registers oct half- rate clock oct control path dff dff 2 hdr block chapter 7: external memory interfaces in stratix iv devices 7?49 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 i/o element registers the ioe registers are expanded to allow so urce-synchronous systems to have faster register-to-register transfers and resynchron ization. both top and bottom and left and right ioes have the same capability. left an d right ioes have extra features to support lvds data transfer. figure 7?31 shows the registers available in the stratix iv input path. the input path consists of the ddr input registers, resynchronization registers, and hdr block. you can bypass each block of the input path. figure 7?31. stratix iv ioe input registers (1) notes to figure 7?31 : (1) you can bypass each regist er block in this path. (2) this is the 0-phase resynchronization cl ock (from the read-leveling delay chain). (3) the input clock can be from the dqs logi c block (whether the postamble circuitry is bypassed or not) or from a global clock line. (4) this input clock comes from the cqn logic block. (5) this resynchronization clo ck comes from a pll through th e clock network (resync_ck_2x). (6) the i/o clock divider resides adjacent to the dqs logi c block. in addition to the pll an d read-leveled resync clock, the i/o clock divider can also be fed by the dqs bus or cqn bus. (7) the half-rate data and clock signals feed into a dual-p ort ram in the fpga core. (8) you can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data rate register to feed dataout . (9) the dqs and dqsn signals must be inverte d for ddr, ddr2, and ddr3 interfaces. when using altera?s memory interface ips, the dqs and dqsn signals are automatically inverted. (10) the bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/ synchronization register to feed dataout . 1 cqn (4) dff i dff input reg a input reg b neg_reg_out i i dq dq 0 dqs/cq (3), (9) dq input reg c dff dq double data rate input registers dqsn (9) differential input buffer dff dff dq dq dff dq dff dff dq dq dff dq alignment & synchronization registers half data rate registers to core dataout[2] (7) to core dataout [0] (7) to core dataout [3] (7) to core dataout [1] (7) to core (7) 0 1 dataoutbypass (8) (2) dff d q dff dq dff dq dff dq dff dq dff dq dff dq dff dq 0 1 7?50 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 there are three registers in the ddr input re gisters block. two registers capture data on the positive and negative edges of the clock, while the third register aligns the captured data. you can choose to use th e same clock for the positive edge and negative edge registers, or two compleme ntary clocks (dqs/cq for the positive-edge register and dqsn/cqn for the negative-edge register). the third register that aligns the captured data uses the same cl ock as the positive edge registers. the resynchronization registers consist of up to three levels of registers to resynchronize the data to the system clock domain. these registers are clocked by the resynchronization clock that is either gene rated by the pll or the read-leveling delay chain. the outputs of the resynchronization re gisters can go straight to the core or to the hdr blocks, which are clocked by the divided-down resynchronization clock. for more information about the read -leveling delay chain, refer to ?leveling circuitry? on page 7?46 . figure 7?32 shows the registers available in th e stratix iv output and output-enable paths. the path is divided into the hdr block, resynchronization registers, and output and output-enable registers. the devi ce can bypass each block of the output and output-enable path. 7?51 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 figure 7?32. stratix iv ioe output and output-enable path registers (1) notes to figure 7?32 : (1) you can bypass each register block of the output and output-enable paths. (2) data coming from the fpga core are at half the frequency of the memory interface clock frequency in half-rate mode. (3) the half-rate clock comes from the pll, while the alig nment clock comes from the write-leveling delay chains. (4) these registers are only u sed in ddr3 sdram interfac es for write-leveling purposes. (5) the write clock can come from either the pll or from the write-leveling dela y chain. the dq write clock and dqs write clock have a 90 offset between them. alignment registers (4) dff dff dq dq dff dq dff dff dq dq dff dq half data rate to single data rate output registers dff dff dq dq dff dq half data rate to single data rate output-enable registers alignment registers (4) alignment clock (3) 0 1 0 1 0 1 from core (2) from core (2) from core (wdata2) (2) from core (wdata0) (2) from core (wdata3) (2) from core (wdata1) (2) dq dff dq dff 0 1 output reg ao output reg bo dq dff dq dff or2 tri oe reg b oe oe reg a oe 0 1 double data rate output-enable registers double data rate output registers dq or dqs write clock (5) half-rate clock (3) dff dq dff dq dff dq dff dq dff dq dff dq dff dq dff dq dff dq 7?52 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 the output path is designed to route combinatorial or registered sdr outputs and full-rate or half-rate ddr outputs from the fpga core. half-rate data is converted to full-rate using the hdr block, clocked by the half-rate clock from the pll. the resynchronization registers are also clocked by the same 0 system clock, except in the ddr3 sdram interface. in ddr3 sdram interfaces, the leveling registers are clocked by the write-leveling clock. for more information about the write-leveling delay chain, refer to ?leveling circuitry? on page 7?46 . the output-enable path has a structure similar to the output path. you can have a combinatorial or registered output in sdr applications and you can use half-rate or full-rate operation in ddr applicatio ns. also, the ouput-enable path?s resynchronization registers have a structur e similar to the output path registers, ensuring that the output-enable path goes through the same delay and latency as the output path. delay chain stratix iv devices have run-time adjustable delay chains in the i/o blocks and the dqs logic blocks. you can control the delay chain setting through the i/o or the dqs configuration block output. figure 7?33 shows the delay chain ports. every i/o block contains the following: two delay chains in a series between the output registers and the output buffer one delay chain between the input buffer and the input register two delay chains between the output enable and the output buffer two delay chains between the oct r t enable control register and the output buffer figure 7?33. delay chain t datain datao u t delayctrlin [3..0] t finedelayctrlin < use finedelayctrlin > 0 1 chapter 7: external memory interfaces in stratix iv devices 7?53 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 figure 7?34 shows the delay chains in an i/o block. each dqs logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input. figure 7?35 shows the delay chains in the dqs input path. figure 7?34. delay chains in an i/o block figure 7?35. delay chains in the dqs input path (o u tp u tdelaysetting2 + o u tp u tfinedelaysetting2) octdelaysetting1 (only) d5 oct delay chain rtena oe octdelaysetting2 (only) (o u tp u tdelaysetting1 + o u tp u tfinedelaysetting1) 0 1 (padtoinp u tregisterdelaysetting + padtoinp u tregisterfinedelaysetting) (o u tp u tdelaysetting2 + o u tp u tfinedelaysetting2) or (o u tp u tonlydelaysetting2 + o u tp u tonlyfinedelaysetting2) d6 oct delay chain d5 o u tp u t- ena b le delay chain d6 o u tp u t- ena b le delay chain d6 delay delay chain d5 delay delay chain d1 delay delay chain (d q s bu so u tdelaysetting + d q s bu so u tfinedelaysetting) d q s bu so u t (d q sena b ledelaysetting + d q sena b lefinedelaysetting) dqs delay chain dqs ena b le control dqs ena b le d q sin d q sena b le dqs d4 delay chain t11 delay chain 7?54 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 i/o configuration block an d dqs configuration block the i/o configuration block and the dqs conf iguration block are shift registers that you can use to dynamically change the setti ngs of various device configuration bits. the shift registers power-up low. every i/o pin contains one i/o configuration register, while every dqs pin contains one dq s configuration block in addition to the i/o configuration register. figure 7?36 shows the i/o configuration block and the dqs configuration block circuitry. table 7?19 lists the i/o configuration block bit sequence. table 7?20 lists the dqs configuration block bit sequence. figure 7?36. i/o configuration block and dqs configuration block table 7?19. i/o configuration block bit sequence bit bit name 0..3 outputdelaysetting1[0..3] 4..6 outputdelaysetting2[0..2] 7..10 padtoinputregisterdelaysetting[0..3] table 7?20. dqs configuration block bit sequence (part 1 of 2) bit bit name 0..3 dqsbusoutdelaysetting[0..3] 4..6 dqsinputphasesetting[0..2] 7..10 dqsenablectrlphasesetting[0..3] 11..14 dqsoutputphasesetting[0..3] 15..18 dqoutputphasesetting[0..3] 19..22 resyncinputphasesetting[0..3] 23 dividerphasesetting 24 enaoctcycledelaysetting 25 enainputcycledelaysetting 26 enaoutputcycledelaysetting 27..29 dqsenabledelaysetting[0..2] 30..33 octdelaysetting1[0..3] datain u pdate ena clk msb b it 0 b it 1 b it 2 chapter 7: external memory interfaces in stratix iv devices 7?55 stratix iv external memory interface features february 2011 altera corporation stratix iv device handbook volume 1 document revision history table 7?21 lists the revision history for this chapter. 34..36 octdelaysetting2[0..2] 37 enadataoutbypass 38 enadqsenablephasetransferreg 39 enaoctphasetransferreg 40 enaoutputphasetransferreg 41 enainputphasetransferreg 42 resyncinputphaseinvert 43 dqsenablectrlphaseinvert 44 dqoutputphaseinvert 45 dqsoutputphaseinvert table 7?20. dqs configuration block bit sequence (part 2 of 2) bit bit name table 7?21. document revision history (part 1 of 2) date version changes february 2011 3.2 updated table 7?5 , table 7?6 , table 7?11 , table 7?19 , and table 7?20 . added table 7?12 . updated figure 7?36 . removed table 7-1 and table 7-6. applied new template. minor text edits. march 2010 3.1 updated figure 7?8, figure 7?11, figure 7?23, figure 7?24, figure 7?29, figure 7?31, and figure 7?36. added figure 7?9 and figure 7?12. added table 7?7. updated table 7?1, table 7?2, table 7?3, table 7?4, table 7?6, table 7?8 and table 7?19. added note to the ?memory interfaces pin support? section. changed ?dll1 through dll4? to ?dll0 through dll3? throughout. added frequency mode 7 throughout. minor text edits. 7?56 chapter 7: external memory interfaces in stratix iv devices stratix iv external memo ry interface features stratix iv device handbook february 2011 altera corporation volume 1 november 2009 3.0 updated the ?memory interfaces pin support? and ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? sections. updated table 7?1, table 7?2, table 7?7, and table 7?12. updated figure 7?3, figure 7?4, figure 7?5, figure 7?6, figure 7?7, figure 7?8, figure 7?9, figure 7?10, figure 7?11, fi gure 7?13, figure 7?14, figure 7?15, and figure 7?16. added figure 7?12 and figure 7?17. added table 7?14, table 7?17, table 7?19, and table 7?20. added ?delay chain? and ?i/o configuration block and dqs configuration block? sections. removed figure 7-8 and figure 7-12. removed table 7-1, table 7-2, and table 7-24. minor text edits. june 2009 2.3 updated ?overview? and ?leveling circuitry?. updated figure 7?26 and figure 7?27. updated table 7?3. added introductory sentences to improve search ability. removed the conclusion section. april 2009 2.2 updated table 7?5, table 7?6, table 7?15, and table 7?17 removed figure 7-12, figure 7-13, and figure 7-20 march 2009 2.1 updated table 7?1, table 7?5, table 7?8, table 7?12, table 7?13, table 7?14, table 7?15, and table 7?17. replaced table 7?6. added table 7?11 and table 7?16. updated figure 7?3, figure 7?6, figure 7?8, figure 7?9, and figure 7?11. added figure 7?7, figure 7?11, figure 7?12, figure 7?13, and figure 7?20. updated ?combining 16/18 dqs/dq groups for 36 qdr ii+/qdr ii sram interface?. updated ?rules to combine groups?. removed ?referenced documents? section. november 2008 2.0 updated table 7?1, table 7?2, table 7?3, table 7?4, table 7?5, and table 7?6. added table 7?7. updated figure 7?1 and figure 7?19. updated ?combining 16/18 dqs/dq groups for 36 qdr ii+/qdr ii sram interface? on page 7?26. updated ?rules to combine groups? on page 7?27. updated ?dqs phase-shift circuitry? on page 7?29. updated table 7?9, table 7?10, table 7?11, table 7?13, table 7?13, table 7?14, table 7?15, table 7?15, table 7?16, and table 7?18. updated figure 7?30 and figure 7?31. made minor editorial changes. may 2008 1.0 initial release. table 7?21. document revision history (part 2 of 2) date version changes siv51008-3.4 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 september 2012 feedback subscribe iso 9001:2008 registered 8. high-speed differential i/o interfaces and dpa in stratix iv devices this chapter describes the significant advant ages of the high-speed differential i/o interfaces and the dynamic phase aligner (dpa) over single-ended i/os and their contribution to the overall system bandwidth achievable with stratix ? iv fpgas. all references to stratix iv devices in this chapter apply to stratix iv e, gt, and gx devices. the stratix iv device family consists of the stratix iv e (enhanced) devices without high-speed clock data recovery (cdr) based transceivers, stratix iv gt devices with up to 48 cdr-based transceivers running up to 11.3 gbps, and stratix iv gx devices with up to 48 cdr-based transceivers running up to 8.5 gbps. the following sections describe the stratix i v high-speed differential i/o interfaces and dpa: ?locations of the i/o banks? on page 8?3 ?lvds channels? on page 8?4 ?lvds serdes? on page 8?8 ?altlvds port list? on page 8?9 ?differential transmitter? on page 8?11 ?differential receiver? on page 8?17 ?lvds interface with the use external pll option enabled? on page 8?26 ?left and right plls (pll_lx and pll_rx)? on page 8?29 ?stratix iv clocking? on page 8?30 ?source-synchronous timi ng budget? on page 8?31 ?differential pin placement guidelines? on page 8?38 overview all stratix iv e, gx, and gt devices have built-in serializer/deserializer (serdes) circuitry that supports high-speed lvds inte rfaces at data rates of up to 1.6 gbps. serdes circuitry is configurable to su pport source-synchronous communication protocols such as utopia, rapid i/o, xsbi, sm all form factor interface (sfi), serial peripheral interface (spi), and asynchrono us protocols such as sgmii and gigabit ethernet. september 2012 siv51008-3.4 8?2 chapter 8: high- speed differential i/o interfaces and dpa in stratix iv devices overview stratix iv device handbook september 2012 altera corporation volume 1 the stratix iv device family has the following dedicated circuitry for high-speed differential i/o support: differential i/o buffer transmitter serializer receiver deserializer data realignment dpa synchronizer (fifo buffer) phase-locked loops (plls) (located on left and right sides of the device) for high-speed differential interfaces, the stratix iv device family supports the following differential i/o standards: lvds mini-lvds reduced swing differential signaling (rsds) in the stratix iv device family, i/os are divided into row and column i/os. figure 8?1 shows i/o bank support for the stratix iv device family. the row i/os provide dedicated serdes circuitry. figure 8?1. i/o bank support in the stratix iv device family (1) , (2) , (3) , (4) notes to figure 8?1 : (1) column input buffers are true lvds buffers, but do not support 100- ?? differential on-chip termination. (2) column output buffers are single ended and need external term ination schemes to support lvds, mini-lvds, and rsds standards. for more information, refer to the i/o features in stratix iv devices chapter. (3) row input buffers are true lvds buffers and support 100- ?? differential on-chip termination. (4) row output buffers are true lvds buffers. lvds i/os row i/os with dedicated serdes circuitry (3), (4) lvds interface with 'use external pll' option disabled lvds interface with 'use external pll' option enabled column i/os (1), (2) chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?3 locations of the i/o banks september 2012 altera corporation stratix iv device handbook volume 1 the altlvds transmitter and receiver requir es various clock and load enable signals from a left or right pll. the quartus ? ii software provides the following two choices when configuring the lvds serdes circuitry when using the pll: lvds interface with the use external pll option enabled?you control the pll settings, such as dynamically reconfiguring the pll to support different data rates, dynamic phase shift, and so on. you must enable the use external pll option in the altlvds_tx and altl vds_rx megafunctions, using the altlvds megawizard ? plug-in manager software. you also must instantiate an altpll megafunction to generate the vari ous clocks and load enable signals. for more information, refer to ?lvds interface with the use external pll option enabled? on page 8?26 . lvds interface with the use external pll option disabled?the quartus ii software configures the pll settings automatically. the software is also responsible for generating the various clock and load enable signals based on the input reference clock and data rate selected. 1 both choices target the same physical pll; the only difference is the additional flexibility provided when an lvds interface has the use external pll option enabled. locations of the i/o banks stratix iv i/os are divided into 16 to 24 i/o banks. the dedicated circuitry that supports high-speed differential i/os is located in banks in the right and left side of the device. figure 8?2 shows a high-level chip overvi ew of the stratix iv e device. figure 8?2. high-speed differential i/os with dpa locations in stratix iv e devices fpga fabric (logic elements, dsp, embedded memory, pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface pll pll pll pll pll pll pll pll clock networks) pll general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr 8?4 chapter 8: high- speed differential i/o interfaces and dpa in stratix iv devices lvds channels stratix iv device handbook september 2012 altera corporation volume 1 figure 8?3 shows a high-level chip overview of the stratix iv gt and gx devices. lvds channels the stratix iv device family supports lvds on both row and column i/o banks. row i/os support true lvds input with 100- ? differential input termination (oct r d ), and true lvds output buffers. column i/os supports true lvds input buffers without oct r d . alternately, you can configure the row and column lvds pins as emulated lvds output buffers that use tw o single-ended output buffers with an external resistor network to support lvds, mini-lvds, and rsds standards. stratix iv devices offer single-ended i/o refclk support for the lvds. dedicated serdes and dpa circuitries are implemented on the row i/o banks to further enhance lvds interface performance in the device. for column i/o banks, serdes is implemented in the core logic because there is no dedicated serdes circuitry on column i/o banks. 1 emulated differential output buffers support tri-state capability starting with the quartus ii software version 9.1. figure 8?3. high-speed differential i/os with dpa locations in stratix iv gt and gx devices pci express hard ip block fpga fabric (logic elements, dsp, embedded memory, pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface transceiver block transceiver block transceiver block transceiver block pci express hard ip block pci express hard ip block pci express hard ip block pll pll pll pll pll pll pll pll clock networks) pll transceiver block transceiver block transceiver block transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?5 lvds channels september 2012 altera corporation stratix iv device handbook volume 1 table 8?1 and table 8?2 list the maximum number of row and column lvds i/os supported in stratix iv e devices. you can design the lvds i/os as true lvds buffers or emulated lvds buffers, as long as th e combination of the two do not exceed the maximum count. for example, there are a total of 112 lvds pairs on row i/os in the 780-pin ep4se230 device (refer to table 8?1 ). you can design up to a maximum of 56 true lvds input buffers and 56 true lvds output buffers, or up to a maximum of 112 emulated lvds output buffers. for the 780-pin ep4se230 device (refer to table 8?2 ), there are a total of 128 lvds pairs on column i/os. you can design up to a maximum of 64 true lvds input buffers and 64 emulated lvds output buffers, or up to a maximum of 128 emulated lvds output buffers. table 8?1. lvds channels supported in stratix iv e device row i/o banks (1) , (2) , (3) device 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga 1760- pin fineline bga ep4se230 56 rx or etx + 56 tx or etx ??? ep4se360 56 rx or etx + 56 tx or etx (4) 88 rx or etx + 88 tx or etx ?? ep4se530 ? 88 rx or etx + 88 tx or etx (5) 112 rx or etx + 112 tx or etx (6) 112 rx or etx + 112 tx or etx ep4se820 ? 88 rx or etx + 88 tx or etx 112 rx or etx + 112 tx or etx 132 rx or etx + 132 tx or etx notes to table 8?1 : (1) receiver (rx) = true lvds input buffers with oct r d , transmitter (tx) = true lvds output buffers, etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divi ded between the left and right sides of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) ep4se360 devices are offered in the h 780 package instead of the f780 package. (5) ep4se530 devices are offered in the h 1152 package instead of the f1152 package. (6) ep4se530 devices are offered in the h 1517 package instead of the f1517 package. table 8?2. lvds channels supported in stratix iv e device column i/o banks (1) , (2) , (3) device 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga 1760-pin fineline bga ep4se230 64 rx or etx + 64 etx ? ? ? ep4se360 64 rx or etx + 64 etx (4) 96 rx or etx + 96 etx ? ? ep4se530 ? 96 rx or etx + 96 etx (5) 128 rx or etx + 128 etx (6) 128 rx or etx + 128 etx ep4se820 ? 96 rx or etx + 96 etx 128 rx or etx + 128 etx 144 rx or etx + 144 etx notes to table 8?2 : (1) rx = true lvds input buffers without oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divi ded between the top and bo ttom sides of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) ep4se360 devices are offered in the h 780 package instead of the f780 package. (5) ep4se530 devices are offered in the h 1152 package instead of the f1152 package. (6) ep4se530 devices are offered in the h 1517 package instead of the f1517 package. 8?6 chapter 8: high- speed differential i/o interfaces and dpa in stratix iv devices lvds channels stratix iv device handbook september 2012 altera corporation volume 1 table 8?3 and table 8?4 list the maximum number of row and column lvds i/os supported in stratix iv gt devices. table 8?5 and table 8?6 list the maximum number of row and column lvds i/os supported in stratix iv gx devices. table 8?3. lvds channels supported in stratix iv gt device row i/o banks (1) , (2) device 1517-pin fineline bga 1932-pin fineline bga ep4s40g2 46 rx or etx + 73 tx or etx ? ep4s40g5 46 rx or etx + 73 tx or etx ? ep4s100g2 46 rx or etx + 73 tx or etx ? ep4s100g3 ? 47 rx or etx + 56 tx or etx ep4s100g4 ? 47 rx or etx + 56 tx or etx ep4s100g5 46 rx or etx + 73 tx or etx 47 rx or etx + 56 tx or etx notes to table 8?3 : (1) rx = true lvds input buffers with oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channel count does not include dedicated clock input pins. table 8?4. lvds channels supported in stratix iv gt device column i/o banks (1) , (2) device 1517-pin fineline bga 1932-pin fineline bga ep4s40g2 96 rx or etx + 96 etx ? ep4s40g5 96 rx or etx + 96 etx ? ep4s100g2 96 rx or etx + 96 etx ? ep4s100g3 ? 128 rx or etx + 128 etx ep4s100g4 ? 128 rx or etx + 128 etx ep4s100g5 96 rx or etx + 96 etx 128 rx or etx + 128 etx notes to table 8?4 : (1) rx = true lvds input buffers without oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channel count does not include dedicated clock input pins. table 8?5. lvds channels supported in stratix iv gx device row i/o banks (1) , (2) , (3) (part 1 of 2) device 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga (4) 1517-pin fineline bga 1760-pin fineline bga 1932-pin fineline bga ep4sgx70 28 rx or etx + 28 tx or etx ? 56 rx or etx + 56 tx or etx ??? ep4sgx110 28 rx or etx + 28 tx or etx 28 rx or etx + 28 tx or etx 56 rx or etx + 56 tx or etx ??? ep4sgx180 28 rx or etx + 28 tx or etx 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx ?? ep4sgx230 28 rx or etx + 28 tx or etx 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx ?? ep4sgx290 ? (5) 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx 88 rx or etx + 88 tx or etx 98 rx or etx + 98 tx or etx chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?7 lvds channels september 2012 altera corporation stratix iv device handbook volume 1 ep4sgx360 ? (5) 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx 88 rx or etx + 88 tx or etx 98 rx or etx + 98 tx or etx ep4sgx530 ? ? 44 rx or etx + 44 tx or etx (6) 88 rx or etx + 88 tx or etx (7) 88 rx or etx + 88 tx or etx 98 rx or etx + 98 tx or etx notes to table 8?5 : (1) rx = true lvds input buffers with oct r d , tx = true lvds output buffers, etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divided between th e left and right sides of the devi ce, except for the devices in th e 780-pin fineline bga. these devices have the lvds rx and tx located on the left side of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) this package supports pma-only transceiver channels. (5) ep4sgx290 and ep4sgx360 devices are offered in the h780 package inst ead of the f780 package. (6) ep4sgx530 devices are offered in the h 1152 package instead of the f1152 package. (7) ep4sgx530 devices are offered in the h 1517 package instead of the f1517 package. table 8?5. lvds channels supported in stratix iv gx device row i/o banks (1) , (2) , (3) (part 2 of 2) device 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga (4) 1517-pin fineline bga 1760-pin fineline bga 1932-pin fineline bga table 8?6. lvds channels supported in stratix iv gx device column i/o banks (1) , (2) , (3) device 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga (4) 1517-pin fineline bga 1760-pin fineline bga 1932-pin fineline bga ep4sgx70 64 rx or etx + 64 etx ? 64 rx or etx + 64 etx ??? ep4sgx110 64 rx or etx + 64 etx 64 rx or etx + 64 etx 64 rx or etx + 64 etx ??? ep4sgx180 64 rx or etx + 64 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx ?? ep4sgx230 64 rx or etx + 64 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx ?? ep4sgx290 72 rx or etx + 72 etx (5) 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 128 rx or etx + 128 etx 128 rx or etx + 128 etx (8) ep4sgx360 72 rx or etx + 72 etx (5) 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 128 rx or etx + 128 etx 128 rx or etx + 128 etx (8) ep4sgx530 ? ? 96 rx or etx + 96 etx (6) 96 rx or etx + 96 etx (7) 128 rx or etx + 128 etx 128 rx or etx + 128 etx notes to table 8?6 : (1) rx = true lvds input buffers without oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divi ded between the left and right sides of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) this package supports pma-only transceiver channels. (5) ep4sgx290 and ep4sgx360 devices are offered in the h780 package inst ead of the f780 package. (6) ep4sgx530 devices are offered in the h 1152 package instead of the f1152 package. (7) ep4sgx530 devices are offered in the h 1517 package instead of the f1517 package. (8) the quartus ii software version 9.0 does no t support ep4sgx290 and ep4sgx360 devices in the 1932-pin fineli ne bga package. t hese devices will be supported in a future release of the quartus ii software. 8?8 chapter 8: high- speed differential i/o interfaces and dpa in stratix iv devices lvds serdes stratix iv device handbook september 2012 altera corporation volume 1 lvds serdes figure 8?4 shows a transmitter and receiver block diagram for the lvds serdes circuitry in the left and right banks. this diagram shows the interface signals of the transmitter and receiver data path. for more information, refer to ?differential transmitter? on page 8?11 and ?differential receiver? on page 8?17 . figure 8?4. lvds serdes (1) , (2) , (3) notes to figure 8?4 : (1) this diagram shows a shared pll between the transmitter and receiver . if the transmitter and recei ver are not sharing the sa me pll, the two left and right plls are required. (2) in sdr and ddr modes, the data width is 1 and 2 bits, respectively. (3) the tx_in and rx_out ports have a maximum data width of 10 bits. + - + - ioe tx_in 10 serializer 2 ioe ioe supports sdr, ddr, or non-registered datapath din dout lvds transmitter lvds receiver tx_coreclock tx_out rx_in dpa circuitry synchronizer din retimed data dpa clock din dout din dout din dout deserializer bit slip 2 3 (lvds_load_en, diffioclk, tx_coreclock) ioe supports sdr, ddr, or non-registered datapath fpga fabric 10 rx_out (load_en, diffioclk) 2 diffioclk clock mux rx_divfwdclk rx_outclock left/right pll rx_inclock/tx_inclock (lvds_load_en, lvds_diffioclk, rx_outclock 3 lvds_diffioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) 8 serial lvds clock phases lvds clock domain dpa clock domain chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?9 altlvds port list september 2012 altera corporation stratix iv device handbook volume 1 altlvds port list table 8?7 lists the interface signals for an lvds transmitter and receiver. table 8?7. port list of the lvds interface (altlvds) (1) , (2) (part 1 of 3) port name input / output description pll signals pll_areset input asynchronous reset to the lvds transmitter and receiver pll. the minimum pulse width requirement for this signal is 10 ns. lvds transmitter interface signals tx_in[ ] input the data bus width per channel is the same as the serialization factor (sf). input data must be synchronous to the tx_coreclock signal. tx_inclock input reference clock input for the transmitter pll. the altlvds megawizard plug-in mana ger software automatically selects the appropriate pll multiplication factor based on the data rate and reference clock frequency selection. for more information about the allowed frequency range for this reference clock, refer to the ?high-speed i/o specification? section in the dc and switching characteristics for stratix iv devices chapter. tx_enable (3) input this port is instantiated only when you select the use external pll option in the megawizard plug-in manager software. this input port must be driven by the pll instantiated though the altpll megawizard plug-in manager software. tx_out output lvds transmitter serial data output port. tx_out is clocked by a serial clock generated by the left and right pll. tx_outclock output the frequency of this clock is programmable to be the same as the data rate, half the data rate, or one-fourth the data rate. the phase offset of this clock, with respect to the serial data, is programmable in increments of 45. tx_coreclock (3) output fpga fabric-transmitter interface clock. the parallel transmitter data generated in the fpga fabric must be clocked with this clock. this port is not available when you select the use external pll option in the megawizard plug-in manager softwar e. the fpga fabric-transmitter interface clock must be driven by the pll instantiated through the altpll megawizard plug-in manager software. tx_locked output when high, this signal indicates that the transmitter pll is locked to the input reference clock. 8?10 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices altlvds port list stratix iv device handbook september 2012 altera corporation volume 1 lvds receiver interface signals rx_in input lvds receiver serial data input port. rx_inclock input reference clock input for the receiver pll. the altlvds megawizard plug-in mana ger software automatically selects the appropriate pll multiplication factor based on the data rate and reference clock frequency selection. for more information about the allowed frequency range for this reference clock, refer to the ?high-speed i/o specification? section in the dc and switching characteristics for stratix iv devices chapter. rx_channel_data_align input edge-sensitive bit-slip control signal. each rising edge on this signal causes the data re-alignment circuitry to shift the word boundary by one bit. the minimum pulse width requirement is one parallel clock cycle. there is no maximum pulse width requirement. rx_dpll_hold input when low, the dpa tracks any dynamic phase variations between the clock and data. when high, the dpa holds the last locked phase and does not track any dynamic phase variations between the clock and data. this port is not available in non-dpa mode. rx_enable (3) input this port is instantiated only when you select the use external pll option in the megawizard plug-in manager software. this input port must be driven by the pll instantiated though the altpll megawizard plug-in manager software. rx_out[ ] output receiver parallel data output. the data bus width per channel is the same as the deserialization factor (df). the output data is synchronous to the rx_outclock signal in non-dpa and dpa modes. it is synchronous to the rx_divfwdclk signal in soft-cdr mode. rx_outclock output parallel output clock from the receiver pll. the parallel data output from the receiver is synchronous to this clock in non-dpa and dpa modes. this port is not available when you select the use external pll option in the megawizard plug-in manager software. the fpga fabric-receiver interface clock must be driven by the pll instantiated through the altpll megawizard plug-in manager software. rx_locked output when high, this signal indicates that the receiver pll is locked to rx_inclock . rx dpa locked output this signal only indicates an initial dpa lock condition to the optimum phase after power up or reset. this signal is not de-asserted if the dpa selects a new phase out of the eight clock phases to sample the received data. you must not use the rx_dpa_locked signal to determine a dpa loss-of-lock condition. rx_cda_max output data re-alignment (bit slip) roll-over signal. when high for one parallel clock cycle, this signal indicates that the user-programmed number of bits for the word boundary to roll-over have been slipped. rx_divfwdclk output parallel dpa clock to the fpga fabric logic array. the parallel receiver output data to the fpga fabric logic array is synchronous to this clock in soft-cdr mode. this signal is not available in non-dpa and dpa modes. dpa_pll_recal input enable pll calibration dynamically without resetting the dpa circuitry or the pll. table 8?7. port list of the lvds interface (altlvds) (1) , (2) (part 2 of 3) port name input / output description chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?11 differential transmitter september 2012 altera corporation stratix iv device handbook volume 1 f for more information about the lvds transmitter and receiver settings using altlvds_tx and altlvds_rx megafunction, refer to the altlvds megafunction user guide . differential transmitter the stratix iv transmitter has a dedicated circuitry to provide support for lvds signaling. the dedicated circuitry consists of a differential buffer, a serializer, and left and right plls that can be shared be tween the transmitter and receiver. the differential buffer can drive out lvds, mi ni-lvds, and rsds signaling levels. the serializer takes up to 10 bits wide parallel data from the fpga fabric, clocks it into the load registers, and serializes it using shif t registers clocked by the left and right pll before sending the data to the differential buffer. the msb of th e parallel data is transmitted first. 1 when using emulated lvds i/o standards at the differential transmitter, the serdes circuitry must be implemented in logic cells but not hard serdes. dpa_pll_cal_busy output busy signal that is asserted high when the pll calibration occurs. reset signals rx_reset input asynchronous reset to the dpa circuitry and fifo. the minimum pulse width requirement for this reset is one parallel clock cycle. this signal resets dpa and fifo blocks. rx_fifo_reset input asynchronous reset to the fifo between the dpa and the data realignment circuits. the synchronizer block must be reset after a dpa loses lock condition and the data checker shows corrupted received data. the minimum pulse width requirement for this reset is one parallel clock cycle. this signal resets the fifo block. rx_cda_reset input asynchronous reset to the data realignment circuitry. the minimum pulse width requirement for this reset is one parallel clock cycle. this signal resets the data realignment block. notes to table 8?7 : (1) unless stated, signals are valid in all three modes (non-dpa, dpa, and soft-cdr) for a single channel. (2) all reset and control signals are active high. (3) for more information, refer to ?lvds interface with the use external pll option enabled? on page 8?26 . table 8?7. port list of the lvds interface (altlvds) (1) , (2) (part 3 of 3) port name input / output description 8?12 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential transmitter stratix iv device handbook september 2012 altera corporation volume 1 the load enable ( lvds_load_en ) signal and the diffioclk signal (the clock running at serial data rate) generated from pll_lx (left pll) or pll_rx (right pll) clocks the load and shift registers. you can statically set the serialization factor to 3, 4, 6, 7, 8, or 10 using the quartus ii software. the load enable signal is derived from the serialization factor setting. figure 8?5 shows a block diagram of the stratix iv transmitter. you can configure any stratix iv transmitter data channel to generate a source-synchronous transmitter clock output. this flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew. different applications often require specific clock-to-data alignments or specific data-rate-to-clock-r ate factors. the transmitter can output a clock signal at the same rate as the data with a maximum frequency of 800 mhz. the output clock can also be divide d by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor. you can set the phase of th e clock in relation to the data at 0 or 180 (edge or center aligned). the left and right plls ( pll_lx and pll_rx ) provide additional support for other phase shifts in 45 increments. these settings are made statically in the quartus ii megawizard plug-in manager software. figure 8?5. stratix iv transmitter (1) , (2) notes to figure 8?5 : (1) in sdr and ddr modes, the data width is 1 and 2 bits, respectively. (2) the tx_in port has a maximum data width of 10 bits. tx_coreclock fpga fabric tx_in 10 serializer 2 ioe lvds transmitter ioe supports sdr, ddr, or non-registered datapath left/right pll tx_inclock (lvds_load_en, diffioclk, tx_coreclock) 3 lvds clock domain din dout + - tx_out chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?13 differential transmitter september 2012 altera corporation stratix iv device handbook volume 1 figure 8?6 shows the stratix iv transmitter in clock output mode. in clock output mode, you can use an lvds cha nnel as a clock output channel. you can bypass the stratix iv serializer to support ddr ( 2) and sdr (1) operations to achieve a serialization factor of 2 and 1, respectively. the i/o element (ioe) contains two data output registers that ca n each operate in either ddr or sdr mode. figure 8?7 shows the serializer bypass path. figure 8?6. stratix iv transmitter in clock output mode transmitter circuit diffioclk lvds_load_en txclkout? txclkout+ parallel series fpga fabric left/right pll figure 8?7. serializer bypass in stratix iv devices (1) , (2) , (3) notes to figure 8?7 : (1) all disabled blocks an d signals are grayed out. (2) in ddr mode, tx_inclock clocks the ioe register. in sdr mode, data is directly passed through the ioe. (3) in sdr and ddr modes, the data width to the ioe is 1 and 2 bits, respectively. + - tx_coreclock t x _ c o r e c l o c k fpga fabric tx_in 2 serializer s e r i a l i z e r 2 ioe din d i n dout d o u t lvds transmitter ioe supports sdr, ddr, or non-registered datapath tx_out left/right pll l e f t / r i g h t p l l (lvds_load_en, diffioclk, tx_coreclock) ( l v d s _ l o a d _ e n , d i f f i o c l k , t x _ c o r e c l o c k ) 3 8?14 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential transmitter stratix iv device handbook september 2012 altera corporation volume 1 programmable v od and programmable pre-emphasis stratix iv lvds transmitters suppo rt programmable pre-emphasis and programmable v od . pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line. figure 8?8 shows the differential lvds output. figure 8?9 shows the lvds output with pre-emphasis. figure 8?8. differential v od figure 8?9. programmable pre-emphasis (1) note to figure 8?9 : (1) v p ? voltage boost from pre-emphasis. v od ? differential output voltage (peak-peak). single-ended waveform positive channel (p) negative channel (n) ground differential waveform p - n = 0v v od v od v od v cm v od (diff peak - peak) = 2 x v od (single-ended) out out v od v p v p chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?15 differential transmitter september 2012 altera corporation stratix iv device handbook volume 1 pre-emphasis is an important feature for high-speed transmission. without pre-emphasis, the output current is limited by the v od setting and the output impedance of the driver. at high frequency, the slew rate may not be fast enough to reach full v od before the next edge, producing pattern-dependent jitter. with pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate. the overshoot introduced by the extra current happens only during switching and does not ring, unlike the overshoot caused by signal reflection. the amount of pre-emphasis needed depends on the attenuation of the high-frequency component along the transm ission line. the quartus ii software allows four settings for programmable pre-emphasis?zero ( 0 ), low ( 1 ), medium ( 2 ), and high ( 3 ). the default setting is low. the v od is also programmable with four settings: low ( 0 ), medium low ( 1 ), medium high ( 2 ), and high ( 3 ). the default setting is medium low. programmable v od you can statically assign the v od settings from the assignment editor. table 8?8 lists the assignment name for programmable v od and its possible values in the quartus ii software assignment editor. figure 8?10 shows the assignment of programmable v od for a transmit data output from the quartus ii software assignment editor. table 8?8. quartus ii software assignment editor to tx_out assignment name programmable differential output voltage (v od ) allowed values 0, 1, 2, 3 figure 8?10. quartus ii software assignment editor?programmable v od 8?16 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential transmitter stratix iv device handbook september 2012 altera corporation volume 1 programmable pre-emphasis four different settings are allowed for pre-emphasis from the assignment editor for each lvds output channel. table 8?9 lists the assignment name and its possible values for programmable pre-emphasis in th e quartus ii software assignment editor. figure 8?11 shows the assignment of programmabl e pre-emphasis for a transmit data output port from the quartus ii software assignment editor. table 8?9. quartus ii software assignment editor to tx_out assignment name programmable pre-emphasis allowed values 0, 1, 2, 3 figure 8?11. quartus ii software assignment editor ? programmable pre-emphasis chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?17 differential receiver september 2012 altera corporation stratix iv device handbook volume 1 differential receiver the stratix iv device family has a dedi cated circuitry to receive high-speed differential signals in row i/os. figure 8?12 shows the hardware blocks of the stratix iv receiver. the receiver has a differen tial buffer and left and right plls that can be shared between the transmitter and receiver, a dpa block, a synchronizer, a data realignment block, and a deserializer. the differential buffer can receive lvds, mini-lvds, and rsds signal levels, which ar e statically set in the quartus ii software assignment editor. the left and right pll receives the external clock input and generates different phases of the same clock. the dpa block chooses one of the clocks from the left and right pll and aligns the incoming data on each channel. the synchronizer circuit is a 1 bit wide by 6 bit deep fifo buffer that compensates for any phase difference between the dpa clock and the data realignment block. if necessary, the user-controlled data realignment circuitry inserts a single bit of la tency in the serial bit stream to align to the word boundary. the deserializer incl udes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic. the stratix iv device family suppor ts three different receiver modes: ?non-dpa mode? on page 8?22 ?dpa mode? on page 8?24 ?soft-cdr mode? on page 8?25 the physical medium connecting the transmitter and receiver lvds channels may introduce skew between the serial data and the source-synchronous clock. the instantaneous skew between each lvds channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver. the three different modes? non-dpa, dpa, and soft-cdr?provide diff erent options to overcome skew between the source synchronous clock (non-dpa, dpa) /reference clock (soft-cdr) and the serial data. 1 only non-dpa mode requires manual skew adjustment. 8?18 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook september 2012 altera corporation volume 1 non-dpa mode allows you to statically se lect the optimal phase between the source synchronous clock and the received serial da ta to compensate skew. in dpa mode, the dpa circuitry automatically chooses the be st phase to compensate for the skew between the source synchronous clock and th e received serial data. soft-cdr mode provides opportunities for synchronous and asynchronous applications for chip-to-chip and short reach board-to-board applications for sgmii protocols. differential i/o termination the stratix iv device family provides a 100- ?? on-chip differential termination option on each differential receiver channel for lvds standards. on-chip termination saves board space by eliminating the need to add external resistors on the board. you can enable on-chip termination in the quartus ii software assignment editor. on-chip differential termination is supported on all row i/o pins and dedicated clock input pins ( clk[0,2,9,11] ). it is not supported for column i/o pins, dedicated clock input pins ( clk[1,3,8,10] ), or the corner pll clock inputs. figure 8?12. receiver block diagram (1) , (2) notes to figure 8?12 : (1) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (2) the rx_out port has a maximum data width of 10 bits. ioe 2 deserializer bit slip synchronizer dpa circuitry 2 clock mux 8 serial lvds clock phases left/right pll rx_inclock lvds clock domain dpa clock domain 10 dout din dout din dout din din retimed data dpa clock lvds_diffiioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out rx_divfwdclk rx_outclock rx_in + fpga fabric lvds receiver ioe supports sdr, ddr, or non-registered datapath chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?19 differential receiver september 2012 altera corporation stratix iv device handbook volume 1 figure 8?13 shows device on-chip termination. receiver hardware blocks the differential receiver has the following hardware blocks: ?dpa block? on page 8?19 ?synchronizer? on page 8?20 ?data realignment block (bit slip)? on page 8?20 ?deserializer? on page 8?22 dpa block the dpa block takes in high-speed serial data from the differential input buffer and selects one of the eight phases generated by the left and right pll to sample the data. the dpa chooses a phase closest to the phase of the serial data. the maximum phase offset between the received data and the selected phase is 1/8 ui, which is the maximum quantization error of the dpa. th e eight phases of the clock are equally divided, offering a 45 resolution. figure 8?14 shows the possible phase relationships between the dpa clocks and the incoming serial data. figure 8?13. on-chip differential i/o termination lvds transmitter stratix iv differential receiver with on-chip 100 termination r d z 0 = 50 z 0 = 50 note to figure 8?14 : (1) t vco is defined as the pll serial clock period. 45? 90? 135? 180? 225? 270? 315? 0.125t vco t vco 0? rx_in d0 d1 d2 d3 d4 dn 8?20 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook september 2012 altera corporation volume 1 the dpa block continuously monitors the phase of the incoming serial data and selects a new clock phase if needed. you can prevent the dpa from selecting a new clock phase by asserting the optional rx_dpll_hold port, which is available for each channel. dpa circuitry does not require a fixed traini ng pattern to lock to the optimum phase out of the eight phases. after reset or powe r up, dpa circuitry requires transitions on the received data to lock to the optimum phase. an optional output port, rx_dpa_locked , is available to indicate an initial dpa lock condition to the optimum phase after power up or reset. this signal is not de-asserted if the dpa selects a new phase out of the eight clock phases to sa mple the received data. do not use the rx_dpa_locked signal to determine a dpa loss-of-lock condition. use data checkers such as a cyclic redundancy check (crc) or diagonal interleave d parity (dip-4) to validate the data. an independent reset port, rx_reset , is available to reset the dpa circuitry. dpa circuitry must be retrained after reset. 1 the dpa block is bypassed in non-dpa mode. synchronizer the synchronizer is a 1 bit wide and 6 bit deep fifo buffer that compensates for the phase difference between dpa_diffioclk , which is the optimal clock selected by the dpa block, and lvds_diffioclk , which is produced by the left and right pll. the synchronizer can only compensate for phase differences, not frequency differences between the data and the receiver?s input reference clock. an optional port, rx_fifo_reset , is available to the internal logic to reset the synchronizer. the synchronizer is automatically reset when the dpa first locks to the incoming data. altera recommends using rx_fifo_reset to reset the synchronizer when the dpa signals a loss-of-lock condition and the data checker indicates corrupted received data. 1 the synchronizer circuit is bypassed in non-dpa and soft-cdr mode. data realignment block (bit slip) skew in the transmitted data along wi th skew added by the link causes channel-to-channel skew on the received seri al data streams. if the dpa is enabled, the received data is captured with differen t clock phases on each channel. this may cause the received data to be misaligned fr om channel to channel. to compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream. an optional rx_channel_data_align port controls the bit insertion of each receiver independently controlled from the internal logic. the data slips one bit on the rising edge of rx_channel_data_align . the requirements for the rx_channel_data_align signal include: the minimum pulse width is one period of the parallel clock in the logic array. the minimum low time between pulses is one period of the parallel clock. this is an edge-triggered signal. chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?21 differential receiver september 2012 altera corporation stratix iv device handbook volume 1 valid data is available two parallel cl ock cycles after the rising edge of rx_channel_data_align . figure 8?15 shows receiver output ( rx_out ) after one bit slip pulse with the deserialization factor set to 4 . the data realignment circuit ca n have up to 11 bit-times of insertion before a rollover occurs. the programmable bit rollover po int can be from 1 to 11 bit-times, independent of the deserialization factor. the programmable bit ro llover point must be set equal to or greater than the deserialization factor, allowing enough depth in the word alignment circuit to sl ip through a full word. you can set the value of the bit rollover point using the megawizard plug-i n manager software. an optional status port, rx_cda_max , is available to the fpga fabric from each channel to indicate when the preset rollover point is reached. figure 8?16 shows a preset value of four bit- times before rollover occurs. the rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has occurred. figure 8?15. data realignment timing rx_in rx_outclock rx_channel_data_align rx_out rx_inclock 3 3210 321x xx21 0321 2 1 0 3 2 1 0 3 2 1 0 figure 8?16. receiver data re-alignment rollover rx_outclock rx_channel_data_align rx_cda_max rx_inclock 8?22 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook september 2012 altera corporation volume 1 deserializer you can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the quartus ii software. you can bypass the st ratix iv deserializer in the quartus ii megawizard plug-in manager software to su pport ddr (2) or sdr (1) operations, as shown figure 8?17 . the dpa and data realignment circuit cannot be used when the deserializer is bypassed. the ioe contains tw o data input registers that can operate in ddr or sdr mode. receiver data path modes the stratix iv device family supports three receiver datapath modes?non-dpa mode, dpa mode, and soft-cdr mode. non-dpa mode figure 8?18 shows the non-dpa datapath block diagram. in non-dpa mode, the dpa and synchronizer blocks are disabled. input se rial data is register ed at the rising or falling edge of the serial lvds_diffioclk clock produced by the left and right pll. you can select the rising/falling edge option using the altldvs megawizard plug-in manager software. both data realignment and deserializer blocks are clocked by the lvds_diffioclk clock, which is generated by the left and right pll. figure 8?17. deserializer bypass in stratix iv devices (1) , (2) , (3) notes to figure 8?17 : (1) all disabled blocks an d signals are grayed out. (2) in ddr mode, rx_inclock clocks the ioe register. in sdr mode, data is directly passed through the ioe. (3) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. ioe 2 dese ri a liz e r deserializer b it slip s y nchronize r dpa circ u itr y 2 c lock m u x 8 s erial l v d s c lock phases left/right pll l e f t / r i g h t p l l 2 dout di n dout di n do u t di n di n r etimed d at a dpa c lock l v d s_ diffiioclk dpa _ di ff ioclk 3 ( dpa_l o ad_e n , d pa_diffioclk , rx_di v f w dclk ) (l v d s _l o ad_e n , l v ds_diffioclk, rx_o u tclk ) 3 ( load_e n , diffioclk ) di ff ioclk rx_o u t r x _ di v f w dclk rx_o u tc l oc k rx_in + fpga fabric lvds receiver ioe s u pports sdr, ddr, or n on-registered datapath chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?23 differential receiver september 2012 altera corporation stratix iv device handbook volume 1 1 when using non-dpa receivers, you must drive the pll from a dedicated and compensated clock input pin. compensated clock inputs ar e dedicated clock pins in the same i/o bank as the pll. f for more information about dedicated and compensated clock inputs, refer to the clock networks and plls in stratix iv devices chapter. figure 8?18. receiver data path in non-dpa mode (1) , (2) notes to figure 8?18 : (1) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (2) the rx_out port has a maximum data width of 10 bits . 2 deserializer bit slip synchroni z er d p a circuitr p p y 2 clock mux 8 s e r ial l vds l l c loc k phases left/right pll rx_inclock lvds clock domain 10 dout din dout din do u t din n din r etimed d ata dp a cloc p p k l vds_diffiioclk l l d p a_diffioclk p p 3 (dp a_lo p p a d_en , dp a_diffioclk, p p rx_divfwdclk ) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out r x _ div f wdclk rx_outclock rx_in + fpga fabric lvds receiver i o e s uppo r t s s dr, ddr, or non-registered datapat h i o e 8?24 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook september 2012 altera corporation volume 1 dpa mode figure 8?19 shows the dpa mode datapath, where all the hardware blocks mentioned in ?receiver hardware blocks? on page 8?19 are active. the dpa block chooses the best possible clock ( dpa_diffioclk ) from the eight fast clocks sent by the left and right pll. this serial dpa_diffioclk clock is used for writing the serial data into the synchronizer. a serial lvds_diffioclk clock is used for reading the serial data from the synchronizer. the same lvds_diffioclk clock is used in data realignment and deserializer blocks. figure 8?19. receiver datapath in dpa mode (1) , (2) , (3) notes to figure 8?19 : (1) all disabled blocks an d signals are grayed out. (2) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (3) the rx_out port has a maximum data width of 10 bits . 2 deserializer bit slip synchronizer dpa circuitry 2 clock mux 8 serial lvds clock phases left/right pll rx_inclock lvds clock domain dpa clock domain 10 dout din din retimed data dpa clock lvds_diffiioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out rx_divfwdcl k rx_outclock rx_in + fpga fabric lvds receiver i o e s u pp o r t s s dr, ddr, or non-re g istered datapat h io e dout din dout din chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?25 differential receiver september 2012 altera corporation stratix iv device handbook volume 1 soft-cdr mode the stratix iv lvds channel offers soft-c dr mode to support the gigabit ethernet and sgmii protocols. a receiver pll uses the local clock source for reference. figure 8?20 shows the soft-cdr mode datapath. in soft-cdr mode, the synchronizer block is inactive. the dpa circuitry selects an optimal dpa clock phase to sample the data. use the selected dpa clock for bit-slip operation and deserialization. the dpa bloc k also forwards the selected dpa clock, divided by the deserialization factor called rx_divfwdclk , to the fpga fabric, along with the deserialized data. this clock sign al is put on the periphery clock (pclk) network. when using soft-cdr mode, the rx_reset port must not be asserted after the dpa training is asserted because the dpa will continuously choose new phase taps from the pll to track parts per million (ppm) differences between the reference clock and incoming data. f for more information about periphery clock networks, refer to the clock networks and plls in stratix iv devices chapter. figure 8?20. receiver datapath in soft-cdr mode (1) , (2) , (3) notes to figure 8?20 : (1) all disabled blocks an d signals are grayed out. (2) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (3) the rx_out port has a maximum data width of 10 bits . 2 deserializer bit slip synchronizer dpa circuitry 2 clock mux 8 serial lvds clock phases left/right pll rx_inclock lvds clock domain dpa clock domain 10 dout din dout din dout din din retimed data dpa clock lvds_diffiioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out rx_divfwdclk rx_outclock rx_in + fpga fabric lvds receiver i o e s u pp o r t s s dr, ddr, or non-re g istered datapat h io e 8?26 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices lvds interface with the use ex ternal pll option enabled stratix iv device handbook september 2012 altera corporation volume 1 you can use every lvds channel in soft-cdr mode and can drive the fpga fabric using the periphery clock network in the stratix iv device family. the rx_dpa_locked signal is not valid in soft-cdr mode be cause the dpa continuously changes its phase to track ppm differences between the upstream transmitter and the local receiver input reference clocks. the parallel clock rx_outclock , generated by the left and right pll, is also forwarded to the fpga fabric. lvds interface with the use external pll option enabled the altlvds megawizard plug-in manager software provides an option for implementing the lvds interface with the use external pll option. with this option enabled you can control the pll settings, su ch as dynamically reconfiguring the pll to support different data rates, dynamic phas e shift, and other settings. you also must instantiate an altpll megafunction to gene rate the various clock and load enable signals. when you enable the use external pll option with the altlvds transmitter and receiver, the following signals are required from the altpll megafunction: serial clock input to the serdes of the altlvds transmitter and receiver load enable to the serdes of the altlvds transmitter and receiver parallel clock used to clock the transmitter fpga fabric logic and parallel clock used for the receiver rx_syncclock port and receiver fpga fabric logic asynchronous pll reset port of the altlvds receiver 1 as an example, table 8?10 describes the serial clock output, load enable output, and parallel clock output generated on ports c0 , c1, and c2, respectively, along with the locked signal of the altpll instance. yo u can choose any of the pll output clock ports to generate the interface clocks. f with soft serdes, a different clocking requirement is needed. for more information, refer to the lvds serdes transmitter/receiver (a ltlvds_rx/tx) megafunction user guide . 1 the high-speed clock generated from the pll is intended to clock the lvds serdes circuitry only. do not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted by the pll f out specification. for more information about the f out specification, refer to the dc and switching characteristics for stratix iv devices chapter. table 8?10 lists the signal interface between the output ports of the altpll megafunction and the input ports of the altlvds transmitter and receiver. table 8?10. signal interface between altpll and altlvds_tx and altlvds_rx megafunctions (part 1 of 2) from the altpll megafunction to the altlvds transmitter to the altlvds receiver serial clock output (c0) (1) tx_inclock (serial clock input to the transmitter) rx_inclock (serial clock input) load enable output (c1) tx_enable (load enable to the transmitter) rx_enable (load enable for the deserializer) chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?27 lvds interface with the use external pll option enabled september 2012 altera corporation stratix iv device handbook volume 1 1 the rx_syncclock port is automatically enabled in an lvds receiver in external pll mode. the quartus ii compiler errors out if this port is not connected, as shown in figure 8?21 . when generating the al tpll megafunction, the left/right pll option is configured to set up the pll in lvds mode. figure 8?21 shows the connection between the altpll and altlvds_tx and altlvds_rx megafunctions. parallel clock output (c2) parallel clock used inside the transmitter core logic in the fpga fabric rx_syncclock (parallel clock input) and parallel clock used inside the receiver core logic in the fpga fabric ~(locked) ? pll_areset (asynchronous pll reset port) (2) notes to table 8?10 : (1) the serial clock output (c0) can only drive tx_inclock on the altlvds transmitter and rx_inclock on the altlvds receiver. this clock cannot drive the core logic. (2) the pll_areset signal is automatically enable d for the lvds receiver in external pll mode. th is signal does not exist for lvds transmitter instantiation when the exte rnal pll option is enabled. table 8?10. signal interface between altpll and altlvds_tx and altlvds_rx megafunctions (part 2 of 2) from the altpll megafunction to the altlvds transmitter to the altlvds receiver figure 8?21. lvds interface with the altpll megafunction (1) note to figure 8?21 : (1) instantiation of pll_areset is optional for the altpll instantiation. transmitter core logic tx_coreclk rx_coreclk receiver core logic tx_in tx_inclock tx_enable altpll lvds receiver (altlvds) lvds transmitter (altlvds) fpga fabric c0 inclk0 c1 c2 rx_out rx_inclock rx_enable rx_syncclock pll_areset locked pll_areset 8?28 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices lvds interface with the use ex ternal pll option enabled stratix iv device handbook september 2012 altera corporation volume 1 example 8?1 shows how to generate three output clocks using an altpll megafunction. example 8?1. generating three output clocks using an altpll megafunction lvds data rate = 1 gbps; serialization fa ctor = 10; input reference clock = 100 mhz the following settings are used when generating the three output clocks using an altpll megafunction. the serial clock must be 1000 mhz and the parallel clock must be 100 mhz (serial clock divided by the serialization factor): c0 frequency = 1000 mhz (multiplication factor = 10 and division factor = 1) phase shift = ?180 with respect to the voltage-controlled oscillator (vco) clock duty cycle = 50% c1 frequency = (1000/10) = 100 mhz (multiplication factor = 1 and division factor = 1) phase shift = (10 - 2) 360/10 = 288 [(deserialization factor - 2)/deserialization factor] 360 duty cycle = (100/10) = 10% (100 divided by the serialization factor) c2 frequency = (1000/10) = 100 mhz (multiplication factor = 1 and division factor = 1) phase shift = (?180/10) = ?18 (c0 phase shift divided by the serialization factor) duty cycle = 50% chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?29 left and right plls (pll_lx and pll_rx) september 2012 altera corporation stratix iv device handbook volume 1 the equation 8?1 calculations for phase shift assume that the input clock and serial data are edge aligned. intr oducing a phase shift of ?180 to sampling clock (c0) ensures that the input data is center-align ed with respect to the c0, as shown in figure 8?22 . left and right plls (pll_lx and pll_rx) the stratix iv device family contains up to eight left and right plls with up to four plls located on the left side and four on the right side of the device. the left plls can support high-speed differential i/o banks on the left side; the right plls can support high-speed differential i/o banks on the right side of the device. the high-speed differential i/o receiver and transmitter channels use these left and right plls to generate the parallel clocks ( rx_outclock and tx_outclock ) and high-speed clocks ( diffioclk ). figure 8?2 on page 8?3 and figure 8?3 on page 8?4 show the locations of the left and right plls for stratix iv e, gt, and gx de vices. the pll vco operates at the clock frequency of the data rate. clock switchov er and dynamic reconfiguration are allowed using the left and right pll in high-speed differential i/o support mode. f for more information, refer to the clock networks and plls in stratix iv devices chapter. figure 8?22. phase relationship for external pll interface signals d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 inclk0 vco clk (internal pll clk) c0 (-180 phase shift) c1 (288 phase shift) c2 (-18 phase shift) serial data 8?30 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices stratix iv clocking stratix iv device handbook september 2012 altera corporation volume 1 stratix iv clocking the left and right plls feed into the diff erential transmitter and receive channels through the lvds and dpa clock network. the center left and right plls can clock the transmitter and receive channels above and below them. the corner left and right plls can drive i/os in the banks adjacent to them. figure 8?23 shows center pll clocking in the stratix iv device family. for more information about pll clocki ng restrictions, refer to ?differential pin placement guidelines? on page 8?38 . figure 8?24 shows center and corner pll clocking in the stratix iv device family. for more information about pll clocking restrictions, refer to ?differential pin placement guidelines? on page 8?38 . figure 8?23. lvds/dpa clocks in the stratix iv device family with center plls 4 2 2 2 2 4 4 4 4 4 4 4 quadrant quadrant quadrant quadrant lvds clock center pll_l2 center pll_l3 dpa clock lvds clock dpa clock lvds clock center pll_r2 center pll_r3 dpa clock lvds clock dpa clock figure 8?24. lvds/dpa clocks in the stratix iv device family with center and corner plls 4 2 2 2 2 4 quadrant quadrant quadrant quadrant lvds clock center pll_l2 center pll_l3 lvds clock dpa clock 2 4 2 4 4 4 2 4 2 4 lvds clock center pll_r2 center pll_r3 dpa clock lvds clock dpa clock corner pll_l1 corner pll_l4 dpa clock corner pll_r1 corner pll_r4 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?31 source-synchronous timing budget september 2012 altera corporation stratix iv device handbook volume 1 source-synchronous timing budget this section describes the timing budget, waveforms, and specifications for source-synchronous signaling in the stra tix iv device family. lvds i/o standards enable high-speed data transmission. this high data transmission rate results in better overall system performance. to take advant age of fast system performance, it is important to understand how to analyze timi ng for these high-speed signals. timing analysis for the differential block is different from traditional synchronous timing analysis techniques. instead of focusing on clock-to-output an d setup times, source synchronous timing analysis is based on the skew between the data and the clock signals. high-speed differential data transmission requires the use of timing parameters provided by ic vendors and is strongly infl uenced by board skew, cable skew, and clock jitter. this section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions fo r the stratix iv device family, and how to use these timing parameters to dete rmine a design?s maximum performance. differential data orientation there is a set relationship between an external clock and the incoming data. for operations at 1 gbps and a serialization factor of 10, the external clock is multiplied by 10. you can set phase-alignment in the pll to coincide with the sampling window of each data bit. the data is sampled on the falling edge of the multiplied clock. figure 8?25 shows the data bit orientation of the 10 mode. differential i/o bit position data synchronization is necessary for successful data transmission at high frequencies. figure 8?26 shows the data bit orientation for a channel operation. this figure is based on the following: serialization factor equals the clock multiplication factor edge alignment is selected for phase alignment implemented in hard serdes figure 8?25. bit orientation in the quartus ii software 9 8 7 6 5 4 3 2 1 0 10 l v ds bits msb lsb inclock/o u tclock data in 8?32 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook september 2012 altera corporation volume 1 for other serialization factors, use the quartu s ii software tools to find the bit position within the word. table 8?11 lists the bit positions after deserialization. table 8?11 lists the conventions for di fferential bit naming for 18 differential channels. the msb and lsb positions increase with th e number of channels used in a system. figure 8?26. bit-order and word boundary for one differential channel (1) note to figure 8?26 : (1) these are only functi onal waveforms and are not intend ed to convey ti ming information. previous cycle 76543210 msb lsb tx_outclock tx_out xxxxxxxx xxx xxxxx current cycle next cycle transmitter channel operation (x8 mode) x xxxxxxxx rx_inclock rx_in 76543210 xxx xxxxxxx xxxx x receiver channel operation (x8 mode) rx_outclock rx_out [7..0] x x x x x x x x x x x x x x x x x x x x 7 6 5 4 3 2 1 0 x x x x table 8?11. differential bit naming receiver channel data number internal 8-bit parallel data msb position lsb position 170 2158 32316 43124 53932 64740 75548 86356 97164 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?33 source-synchronous timing budget september 2012 altera corporation stratix iv device handbook volume 1 transmitter channel-to-channel skew transmitter channel-to-channe l skew (tccs) is an important parameter based on the stratix iv transmitter in a source synchronou s differential interface. this parameter is used in receiver skew margin calculation. for more information, refer to ?receiver skew margin for non-dpa mode? on page 8?33 . tccs is the difference between the fastes t and slowest data output transitions, including the tco variation and clock skew. for lvds transmitters, the timequest timing analyzer provides a tccs report, which shows tccs values for serial output ports. f you can get the tccs value from the tccs report ( report_tccs ) in the quartus ii compilation report under the timequest timing analyzer, or from the dc and switching characteristics for stratix iv devices chapter. receiver skew margin for non-dpa mode changes in system environment, such as temperature, media (cable, connector, or pcb), and loading effect the receiver?s setup and hold times; internal skew affects the sampling ability of the receiver. different modes of lvds receivers use different specifications that can help in deciding the ability to sample the received serial data correctly. in dpa mode, you must use dpa jitter tolerance instead of receiver input skew margin (rskm). in non-dpa mode, use tccs, rskm, and samp ling window (sw) specifications for high-speed source-synchronous differential signals in the receiver data path. the relationship between rskm, tccs, and sw is expressed by the rskm equation shown in equation 8?1 . conventions used for the equation: time unit interval (tui)?time period of the serial data. rskm?the timing margin between the rece iver?s clock input and the data input sampling window. sw?the period of time that the input data must be stable to ensure that data is successfully sampled by the lvds receiver. the sw is a device property and varies with device speed grade. tccs?the timing difference between the fastest and the slowest output edges, including t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement. equation 8?1. rskm rskm tui sw ? tccs ? 2 ---------------------------------------------- = 8?34 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook september 2012 altera corporation volume 1 figure 8?27 shows the relationship between the rskm, tccs, and the receiver?s sw. you must calculate the rskm value to deci de whether or not data can be sampled properly by the lvds receiver with the give n data rate and device. a positive rskm value indicates that the lvds receiver can sample the data properly, whereas a negative rskm indicates that it cannot. figure 8?27. differential high-speed timing diagram and timing budget for non-dpa mode tui time unit inter v al (tui) tccs internal clock falling edge tccs tccs 2 recei v er inp u t data transmitter o u tp u t data internal clock synchronization external clock recei v er inp u t data internal clock external inp u t clock timing budge t timing diag r am clock placement s w tccs rskm rskm s w rskm rskm chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?35 source-synchronous timing budget september 2012 altera corporation stratix iv device handbook volume 1 for lvds receivers, the quartus ii softwa re provides an rskm report showing the sw, tui, and rskm values for non-dpa mode. you can generate the rskm report by executing the report_rskm command in the timequest timing analyzer. you can find the rskm report in the quartus ii compil ation report under the timequest timing analyzer section. 1 in order to obtain the rskm value, you must assign an appropriate input delay to the lvds receiver through the timequest timing analyzer constraints menu. for assigning input delay, follow these steps: 1. the quartus ii timequest timing analyz er gui has many options for setting the constraints and analyzing the design. figure 8?28 shows various commands on the constraints menu. for setting in put delay, you must select the set input delay option. figure 8?28. selection of constraint menu in timequest timing analyzer 8?36 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook september 2012 altera corporation volume 1 2. figure 8?29 shows the setting parameters for the set input delay option. the clock name must reference the source synchronous clock that feeds the lvds receiver. select the desired clock using the pull-down menu. 3. figure 8?30 shows the targets option. you can view a list of all available ports using the list option in the name finder window. figure 8?29. input time delay assignment through timequest timing analyzer figure 8?30. name finder window in set input delay option chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?37 source-synchronous timing budget september 2012 altera corporation stratix iv device handbook volume 1 4. select the lvds receiver serial input po rts (from the list) according to the input delay you set. click ok . 5. in the set input delay window, set the appropriate values in the input delay options section and delay value. 6. click run to incorporate these values in the timequest timing analyzer. 7. assign the appropriate delay for all the lvds receiver input ports following these steps. if you have already assigned input delay and you need to add more delay to that input port, use the add delay option in the set input delay window. 1 if no input delay is set in the timequest timing analyzer, the receiver channel-to-channel skew (rccs) defaults to zero. you can also directly set the input delay in a synopsys design constraint file ( .sdc) using the set_input_delay command. f for more information about .sdc commands and the timequest timing analyzer, refer to the quartus ii timequest timing analyzer chapter in volume 3 of the quartus ii development software handbook . example 8?2 shows the rskm calculation. 1 you can also calculate rskm using the steps described in ?guidelines for dpa- enabled differential channels? on page 8?38 . example 8?2. rskm data rate: 1 gbps, board channel-to-channel skew = 200 ps for stratix iv devices: tccs = 100 ps (pending characterization) sw = 300 ps (pending characterization) tui = 1000 ps total rccs = tccs + board channel- to-channel skew= 100 ps + 200 ps = 300 ps rskm= tui - sw - rccs = 1000 ps - 300 ps - 300 ps = 400 ps > 0 because the rskm > 0 ps, receiver non-dpa mode must work correctly. 8?38 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook september 2012 altera corporation volume 1 differential pin placement guidelines to ensure proper high-speed operation, di fferential pin placement guidelines have been established. the quartus ii compiler au tomatically checks that these guidelines are followed and issues an error message if they are not met. this section is divided into pin placemen t guidelines with and without dpa usage because dpa usage adds some constraints on the placement of high-speed differential channels. 1 dpa-enabled differential channels refe r to dpa mode or soft-cdr mode; dpa disabled channels refer to non-dpa mode. guidelines for dpa-enabl ed differential channels the stratix iv device family has differenti al receivers and transmitters in i/o banks on the left and right sides of the device. each receiver has a dedicated dpa circuit to align the phase of the clock to the data phase of its associated channel. when you use dpa-enabled channels in differential banks, you must adhere to the guidelines listed in the following sections. dpa-enabled channels and single-ended i/os when you enable a dpa channel in a bank, both single-ended i/os and differential i/o standards are allowed in the bank. single-ended i/os are allowed in the same i/o bank, as long as the single-ended i/o standard uses the same v ccio as the dpa-enabled differential i/o bank. single-ended inputs can be in the same logic array block (lab) row as a differential channel using the serdes circuitry. ddio can be placed within the same lab row as a serdes differential channel but half rate ddio (single data rate) output pins cannot be placed within the same lab row as a receiver serdes differential channel. the input register must be implemented within the fpga fabric logic. dpa-enabled channel driving distance if the number of dpa channels driven by each left and right pll exceeds 25 lab rows, altera recommends implementing data realignment (bit slip) circuitry for all the dpa channels. using corner and center left and right plls if a differential bank is being driven by tw o left and right plls, where the corner left and right pll is driving one group and the center left and right pll is driving another group, there must be at least one ro w of separation between the two groups of dpa-enabled channels (refer to figure 8?31 ). the two groups can operate at independent frequencies. chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?39 differential pin pl acement guidelines september 2012 altera corporation stratix iv device handbook volume 1 you do not need a separation if a single left and right pll is driving the dpa-enabled channels as well as dpa-disabled channels. figure 8?31. corner and center left and right plls driving dpa-enabled differential i/os in the same bank center left /right pll corner left / right pll diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa -enabled diff i/o dpa- enabled diff i/o channels driven by corner left/right pll channels driven by center left/right pll one unused channel for buffer dpa -enabled diff i/o dpa - enabled diff i/o dpa - enabled diff i/o dpa - enabled diff i/o dpa - enabled diff i/o reference reference clk clk 8?40 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook september 2012 altera corporation volume 1 using both center left and right plls you can use both center left and right plls to drive dpa-enabled channels simultaneously, as long as they drive these channels in their adjacent banks only, as shown in figure 8?32 . if one of the center left and right plls drives the top and bottom banks, you cannot use the other center left and right pll to drive differential channels, as shown in figure 8?32 . if the top pll_l2 and pll_r2 drives dpa-enabled channels in the lower differential bank, the pll_l3 and pll_r3 cannot drive dpa-enabled channels in the upper differential banks and vice versa. in other words, the center left and right plls cannot drive cross-banks simultaneously, as shown in figure 8?33 . figure 8?32. center left and right plls driving dpa-enabled differential i/os reference clk dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o center left/right pll (pll_l2/pll_r2) center left/right pll (pll_l2/pll_r2) center left/right pll (pll_l3/pll_r3) center left/right pll (pll_l3/pll_r3) unused pll reference clk reference clk reference clk dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?41 differential pin pl acement guidelines september 2012 altera corporation stratix iv device handbook volume 1 figure 8?33. invalid placement of dpa-enabled differ ential i/os driven by both center left and right plls dpa-enabled diff i/o center left /right pll dpa-enabled diff i/o dpa-enabled diff i/o reference clk reference clk dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o center left /right pll dpa-enabled diff i/o dpa-enabled diff i/o 8?42 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook september 2012 altera corporation volume 1 guidelines for dpa-disabl ed differential channels when you use dpa-disabled channels in the left and right banks of a stratix iv device, you must adhere to the guidelines in the following sections. 1 when using non-dpa receivers, you must drive the pll from a dedicated and compensated clock input pin. compensated clock inputs ar e dedicated clock pins in the same i/o bank as the pll. f for more information about dedicated and compensated clock inputs, refer to the clock networks and plls in stratix iv devices chapter. dpa-disabled channels and single-ended i/os the placement rules for dpa-disabled channels and single-ended i/os are the same as those for dpa-enabled channels and si ngle-ended i/os. for more information, refer to ?dpa-enabled channels and si ngle-ended i/os? on page 8?38 . dpa-disabled channel driving distance each left and right pll can drive all the dpa-disabled channels in the entire bank. using corner and center left and right plls you can use a corner left and right pll to drive all transmitter channels and a center left and right pll to drive all dpa-disabled receiver channels within the same differential bank. in other words, a transmitter channel and a receiver channel in the same lab row can be driven by two different plls, as shown in figure 8?34 . a corner left and right pll and a center left and right pll can drive duplex channels in the same differential bank, as long as the channels driven by each pll are not interleaved. separation is not necessary be tween the group of channels driven by the corner and center left and right plls, as shown in figure 8?34 and figure 8?35 . chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?43 differential pin pl acement guidelines september 2012 altera corporation stratix iv device handbook volume 1 figure 8?34. corner and center left and right plls driving dpa-disabled differential i/os in the same bank diff rx corner left/right pll diff tx diff rx diff rx diff tx diff tx diff tx diff tx diff tx diff tx diff rx diff rx diff tx diff rx diff rx diff tx diff rx diff rx diff rx diff tx corner left / right pll dpa -disabled diff i /o channels dri v en b y corner left/right pll channels dri v en b y center left/right pll n o separation bu ffer needed reference clk reference clk reference clk reference clk dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o center left/right pll center left/right pll 8?44 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook september 2012 altera corporation volume 1 figure 8?35. invalid placement of dpa-disabled diff erential i/os due to interleaving of channels driven by the corner and center left and right plls dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o corner left/right pll reference clk dpa-disabled diff i/o dpa-disabled diff i/o reference clk center left/right pll chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?45 differential pin pl acement guidelines september 2012 altera corporation stratix iv device handbook volume 1 using both center left and right plls you can use both center left and right plls simultaneously to drive dpa-disabled channels on upper and lower differential banks. unlike dpa-enabled channels, the center left and right plls can drive cross- banks. for example, the upper-center left and right pll can drive the lower differential bank at the same time the lower center left and right pll is driving the upper differ ential bank, and vice versa, as shown in figure 8?36 . figure 8?36. both center left and right plls driving cross-bank dpa-disabled channels simultaneously dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o dpa-disa b led diff i/o reference clk reference clk center left/right pll center left/right pll 8?46 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook september 2012 altera corporation volume 1 document revision history table 8?12 lists the revision history for this chapter. table 8?12. document revision history (part 1 of 2) date version changes september 2012 3.4 updated figure 8?22 to close fb case #.28708. updated the ?soft-cdr mode? section to close fb #41886. december 2011 3.3 updated the ?overview? and ?altlvds port list? sections. updated table 8?10. february 2011 3.2 updated table 8?10. updated the ?differential tran smitter?, ?non-dpa mode?, ?l vds interface with the use external pll option enabled?, ?deserializer?, and ?guidelines for dpa-disabled differential channels? sections. applied new template. minor text edits. march 2010 3.1 removed note 7 from table 8?1 and table 8?2. updated figure 8?5. updated the ?lvds channels? section. updated table 8?7. added a note to the ?lvds interface with the use external pll option enabled? and ?altlvds port list? sections. minor text edits. november 2009 3.0 changed ?dedicated lvds? to ?true lvds?. removed ep4se110, ep4se290, and ep4se680 devices. added ep4se820 and stratix iv gt devices. updated ?lvds channels?, ?differential tr ansmitter?, ?soft-cdr mode?, and ?dpa- enabled channels and single-ended i/os? sections. updated table 8?1, table 8?2, table 8?5, and table 8?6. added table 8?3 and table 8?4. updated example 8?1. updated figure 8?22. minor text edits. june 2009 2.3 added an introductory paragraph to increase search ability. minor text edits. april 2009 2.2 updated ?introduction?. updated figure 8?3. removed table 8-5 and table 8-6. march 2009 2.1 updated ?introduction?, ?stratix iv lvds channe ls?, ?stratix iv diffe rential transmitter?, ?differential i/o termination?, and ?dynamic phase alignment (dpa) block? sections. updated table 8?1, table 8?2, table 8?3, table 8?4, and table 8?7. added table 8?5 and table 8?6. updated figure 8?2. removed ?referenced documents? section. chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?47 differential pin pl acement guidelines september 2012 altera corporation stratix iv device handbook volume 1 november 2008 2.0 updated figure 8?2, figure 8?3, figure 8?21, figure 8?34. removed figure 8?31. updated table 8?1, table 8?10. updated ?differential pin placement guidelines? section. may 2008 1.0 initial release. table 8?12. document revision history (part 2 of 2) date version changes 8?48 chapter 8: hi gh-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook september 2012 altera corporation volume 1 september 2012 altera corporation stratix iv device handbook volume 1 section iii. system integration this section includes the following chapters: chapter 9, hot socketing and power-on reset in stratix iv devices chapter 10, configuration, design secu rity, and remote system upgrades in stratix iv devices chapter 11, seu mitigation in stratix iv devices chapter 12, jtag boundary-scan testing in stratix iv devices chapter 13, power management in stratix iv devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. iii?2 section iii: system integration stratix iv device handbook september 2012 altera corporation volume 1 siv51009-3.2 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 9. hot socketing and power-on reset in stratix iv devices this chapter describes hot-socketing specifications, power-on reset (por) requirements, and their implementation in stratix ? iv devices. stratix iv devices offer hot socketing, also known as hot plug-in or hot swap, and power sequencing support without the use of external devices. you can insert or remove a stratix iv device or a board in a system during system operation without causing undesirable effects to the running syst em bus or board that is inserted into the system. the hot-socketing feature also removes some of the difficulty when you use stratix iv devices on pcbs that contain a mixture of 3.0-, 2.5-, 1.8- , 1.5-, and 1.2-v devices. the stratix iv hot-socketing feature provides: board or device insertion and removal without external components or board manipulation support for any power-up sequen ce with the exception that v cc must power up fully before v ccaux for all stratix iv production devices i/o buffers non-intrusive to syst em buses during hot insertion this section also describes por circuitry in stratix iv devices. por circuitry keeps the devices in the reset state until the power supply outputs are within operating range (provided v cc powers up fully before v ccaux ). this chapter contains the following sections: ?stratix iv hot-socketing specifications? ?hot-socketing feature implementation in stratix iv devices? on page 9?2 ?power-on reset circuitry? on page 9?3 ?power-on reset specifications? on page 9?4 stratix iv hot-socketing specifications stratix iv devices are hot-socketing co mpliant without the need for external components or special design requirements. hot-socketing support in stratix iv devices has the following advantages: ?stratix iv devices can be driv en before power up? on page 9?2 ?i/o pins remain tri-stated during power up? on page 9?2 ?insertion or removal of a stratix iv device from a powered-up system? on page 9?2 february 2011 siv51009-3.2 9?2 chapter 9: hot socketing and power-on reset in stratix iv devices stratix iv hot-socketing specifications stratix iv device handbook february 2011 altera corporation volume 1 stratix iv devices can be driven before power up you can drive signals into i/o pins, dedicated input pins, and dedicated clock pins of stratix iv devices before or during power up or power down without damaging the device. i/o pins remain tri-stated during power up a device that does not support hot socketin g can interrupt system operation or cause contention by driving out before or during power up. in a hot-socketing situation, the stratix iv device?s output buffers are turn ed off during system power up or power down. also, the stratix iv device does not drive out until the device is configured and working within the recommended operating conditions. insertion or removal of a stratix iv device fr om a powered-up system devices that do not support hot socketing can short power supplies when powered up through the device signal pins. this irregular power up can damage both the driving and driven devices and can disrupt card power up. you can insert a stratix iv device into or remove it from a powered-up system board without damaging the system board or interfering with its operation. you can power up or power down the v ccio , v cc , v ccpgm , and v ccpd supplies in any sequence (with any time between them) which are monitored by the hot socket circuit. in addition, all other power supplies for the device can be powered up or down in any sequence. individual power supply ramp-u p and ramp-down rates range from 50 s to 100 ms. during hot socketing, the i/o pin capacitance is less than 15 pf and the clock pin capacitance is less than 20 pf. 1 to successfully power-up and exit por on production devices, fully power v cc before v ccaux begins to ramp. a possible concern regarding hot socketing is the potential for ?latch-up.? stratix iv devices are immune to latch-up when ho t socketing. latch-up can occur when electrical subsystems are hot socketed into an active system. during hot socketing, the signal pins can be connected and driven by the active system before the power supply can provide current to the device?s power an d ground planes. this condition can lead to latch-up and cause a low-impedance path from power to ground within the device. as a result, the device draws a large amount of current, possibly causing electrical damage. chapter 9: hot socketing and power-on reset in stratix iv devices 9?3 hot-socketing feature implemen tation in stratix iv devices february 2011 altera corporation stratix iv device handbook volume 1 hot-socketing feature implementation in stratix iv devices the hot-socketing feature turns off the ou tput buffer during power up and power down of the v cc , v ccaux , v ccio , v ccpgm , or v ccpd power supplies. the hot-socketing circuitry generates an internal hotsckt signal when the v cc , v ccaux , v ccio , v ccpgm , or v ccpd power supplies are below the threshold voltage. hot-socketing circuitry is designed to prevent excess i/o leakage du ring power up. when the voltage ramps up very slowly, it is still relatively low, even after the por signal is released and the configuration is completed. the conf_done , nceo , and nstatus pins fail to respond, as the output buffer cannot flip from the state set by the hot-socketing circuit at this low voltage. therefore, the hot-socketing circuitry has been removed from these configuration pins to make su re that they are able to operate during configuration. thus, it is expected behavior for these pins to drive out during power-up and power-down sequences. figure 9?1 shows the stratix iv device?s i/o pin circuitry. the por circuit monitors the voltage level of the power supplies (v cc , v ccaux , v ccpt , v ccpgm , and v ccpd ) and keeps the i/o pins tri-stated until the device is in user mode. the weak pull-up resistor (r) in the stra tix iv input/output element (ioe) keeps the i/o pins from floating. the 3. 0-v tolerance control circuit permits the i/o pins to be driven by 3.0 v before the v cc , v ccaux , v ccpt , v ccpgm , or v ccpd supplies are powered. it also prevents the i/o pins from driving out when the device is not in user mode. to successfully power-up and exit por on production devices, fully power v cc before v ccaux begins to ramp. 1 altera uses gnd as a reference for hot-sock eting operations and i/o buffer designs. to ensure proper operation, you must connect the gnd between boards before connecting the power supplies. this prevents the gnd on your board from being pulled up inadvertently by a path to powe r through other components on your board. a pulled up gnd could otherwise cause an out-of-specification i/o voltage or current condition with the altera device. figure 9?1. hot-socketing circuitry for stratix iv devices v ccio pa d r voltage tolerance control output enable hot socket output pre-driver power on reset monitor weak pull-up resistor input buffer to logic array 9?4 chapter 9: hot socketing and power-on reset in stratix iv devices power-on reset circuitry stratix iv device handbook february 2011 altera corporation volume 1 power-on reset circuitry when power is applied to a stratix iv devi ce, a por event occurs if the power supply reaches the recommended operating range within the maximum power supply ramp time (t ramp ). if t ramp is not met, the device i/o pins and programming registers remain tri-stated, during which device configuration could fail. the maximum t ramp for stratix iv devices is 100 ms; the minimum t ramp is 50 s. when the porsel pin is high, the maximum t ramp for stratix iv devices is 4 ms. stratix iv devices provide a dedicated input pin ( porsel ) to select a por delay time during power up. when the porsel pin is connected to gnd, the por delay time is 100 to 300 ms. when the porsel pin is set to high, the por delay time is 4 to 12 ms. the por block consists of a regulator por, satellite por, and main por to check the power supply levels for proper device configuration. the satellite por monitors the following: v ccpd and v ccpgm power supplies that are used in the i/o buffers and for device programming v ccaux power supply which is the auxiliary supply for the programmable power technology v cc and v ccpt power supplies that are used in the device core 1 altera requires powering up v cc before v ccaux . the main por waits for satellite por and the regulator por to release the por signal. until the release of the por sign al, the device configuration cannot start. the internal configuration memory supply that is used during device configuration is checked by the regulator por block and is gated in the main por block for the final por trip. figure 9?2 shows a simplified diagram of the por block. 1 all configuration-related dedicated and dual function i/o pins must be powered by v ccpgm . figure 9?2. simplified por diagram for stratix iv devices regulator por satellite por por pulse setting porsel por main por v ccpgm v ccpd v cc v ccpt v ccaux chapter 9: hot socketing and power-on reset in stratix iv devices 9?5 power-on reset specifications february 2011 altera corporation stratix iv device handbook volume 1 power-on reset specifications table 9?1 lists the power supplies that the por circuit monitors. 1 altera requires powering up v cc before v ccaux . table 9?2 lists the power supplies that th e por circuit does not monitor. 1 v ccio , v cca_pll , v ccd_pll , v cc_clkin , and v ccbat are not monitored by por and have no affect on the device configuration. the por specification is designed to ensure th at all the circuits in the stratix iv device are at certain known states during power up. the por signal pulse width is programmable using the porsel input pin. when the porsel pin is connected to gnd, the por de lay time is 100 to 300 ms. when the porsel pin is set to high, the po r delay time is 4 to 12 ms. f for more information about the por specification, refer to the dc and switching characteristics for stratix iv devices chapter. table 9?1. power supplies monitored by the por circuitry power supply description setting (v) v cc core and periphery power supply 0.9 v ccpt programmable power technology power supply 1.5 v ccpd i/o pre-driver power supply 2.5, 3.0 v ccpgm configuration pins power supply 1.8, 2.5, 3.0 v ccaux auxiliary supply for the programmable power technology 2.5 table 9?2. power supplies not monitored by the por circuitry (note 1) power supply description setting (v) v ccio i/o power supply 1.2, 1.5, 1.8, 2.5, 3.0 v cca_pll pll analog global power supply 2.5 v ccd_pll pll digital power supply 0.9 v cc_clkin pll differential clock input power supply (top and bottom i/o banks only) 2.5 v ccbat battery back-up power supply for design security volatile key storage 1.2-3.3 note to table 9?2 : (1) the transceiver supplies are not monitored by por. 9?6 chapter 9: hot socketing and power-on reset in stratix iv devices power-on reset specifications stratix iv device handbook february 2011 altera corporation volume 1 document revision history table 9?3 lists the revision history for this chapter. table 9?3. document revision history date version changes february 2011 3.2 updated table 9?2 . updated the ?power-on reset circuitry? , ?power-on reset specifications? , and ?insertion or removal of a stratix iv device from a powered-up system? sections. applied new template. minor text edits. march 2010 3.1 updated the introduction and the ?stratix iv hot-socketing specifications?, ?insertion or removal of a stratix iv device from a powered-up system?, ?hot-socketing feature implementation in stratix iv devices?, ?pow er-on reset circuitry?, and ?power-on reset specifications? sections. updated table 9?1 and table 9?2. updated figure 9?2. minor text edits. november 2009 3.0 updated graphics. minor text edits. june 2009 2.2 updated table 9?2. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. march 2009 2.1 changed all ?stratix iv e? to ?stratix iv?. updated ?stratix iv hot-socketing specifications? and ?hot-socketing feature implementation in stratix iv devices? sections. updated figure 9?2. removed ?referenced documents? section. november 2008 2.0 updated ?hot-socketing feature implementation in stratix iv devices? on page 9?2. updated ?power-on reset circuitry? on page 9?4. updated table 9?1. made minor editorial changes. july 2008 1.1 revised ?introduction?. may 2008 1.0 initial release. siv51010-3.5 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 september 2012 feedback subscribe iso 9001:2008 registered 10. configuration, design security, and remote system upgrades in stratix iv devices this chapter describes the configuration, design security, and remote system upgrades in stratix ? iv devices. to save configuration memory space and time, stratix iv devices provide configuration data decompression. they also provide a built-in design security feature that protects your designs against ip theft and tampering of your configuration files. stratix iv devices also offer remote system upgrade capability so that you can upgrade your system in real-time through an y network. this helps to deliver feature enhancements and bug fixes and provides error detection, recovery, and status information to ensure reliable reconfiguration. overview this chapter describes supported configuration schemes for stratix iv devices, instructions about how to execute the re quired configuration schemes, and the necessary pin settings. stratix iv devices use sram cells to store configuration data. as sram is volatile, you must download configuration data to th e stratix iv device each time the device powers up. you can configure stratix iv devices using one of four configuration schemes: fast passive parallel (fpp) fast active serial (as) passive serial (ps) joint test action group (jtag) all configuration schemes use either an ex ternal controller (for example, a max ? ii device or microprocessor), a configuration device, or a download cable. for more information, refer to ?configuration features? on page 10?4 . this chapter includes the following sections: ?configuration schemes? on page 10?2 ?configuration features? on page 10?4 ?fast passive parallel configuration? on page 10?6 ?fast active serial configuration (ser ial configuration devices)? on page 10?16 ?passive serial configuration? on page 10?24 ?jtag configuration? on page 10?34 ?device configuration pins? on page 10?39 september 2012 siv51010-3.5 10?2 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices configuration schemes stratix iv device handbook september 2012 altera corporation volume 1 ?configuration data decompression? on page 10?47 ?remote system upgrades? on page 10?49 ?remote system upgrade mode? on page 10?53 ?dedicated remote system up grade circuitry? on page 10?56 ?quartus ii software support? on page 10?62 ?design security? on page 10?63 configuration devices altera ? serial configuration devices support a single-device and multi-device configuration solution for stratix iv devices and are used in the fast as configuration scheme. serial configuration devices offe r a low-cost, low pin-count configuration solution. f for information about serial configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook . 1 all minimum timing information in this chap ter covers the entire stratix iv family. some devices may work at less than the mi nimum timing stated in this handbook due to process variation. configuration schemes select the configuration scheme by driving the stratix iv device msel pins either high or low, as shown in table 10?1 . the msel input buffers are powered by the v cc power supply. altera recommends hard wiring the msel[] pins to v ccpgm and gnd. the msel[2..0] pins have 5-k ? internal pull-down resistor s that are always active. during power-on reset (por) an d during reconfiguration, the msel pins must be at v il and v ih levels of v ccpgm voltage to be considered logic low and logic high. 1 to avoid problems with detecting an inco rrect configuration scheme, hardwire the msel[] pins to v ccpgm and gnd without pull-up or pull -down resistors. do not drive the msel[] pins by a microprocessor or another device. table 10?1. configuration schemes for stratix iv devices (part 1 of 2) configuration scheme msel2 msel1 msel0 fast passive parallel 0 0 0 passive serial 0 1 0 fast as (40 mhz) (1) 011 remote system upgrade fast as (40 mhz) (1) 011 fpp with design security feature and/or decompression enabled (2) 001 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?3 configuration schemes september 2012 altera corporation stratix iv device handbook volume 1 table 10?2 lists the uncompressed raw binary file ( .rbf ) configuration file sizes for stratix iv devices. use the data in table 10?2 to estimate the file size befo re design compilation. different configuration file formats; for example, a hexidecimal ( .hex ) or tabular text file ( .ttf ) format, have different file sizes. refer to the quartus ? ii software for the different types of configuration file and file sizes. however, for any specific version of the quartus ii software, any design targeted for the same device has the same uncompressed configuration file size. if yo u are using compression, the file size can vary after each compilation because the compression ratio depends on the design. jtag-based configuration (4) (3) (3) (3) notes to table 10?1 : (1) stratix iv devices only support fast as configuration. yo u must use either epcs64 or epcs 128 devices to configure a stratix iv device in fast as mode. (2) these modes are only supported when usi ng a max ii device or a microprocessor with flash memory for conf iguration. in these modes, the host system must output a dclk that is 4 the data rate. (3) do not leave the msel pins floating, connect them to v ccpgm or gnd. these pins support the non-jtag configuration scheme used in production. if you only use the jt ag configuration, connect the msel pins to gnd. (4) the jtag-based configuration takes precedence o ver other configuration schemes, which means the msel pin settings are ignored. the jtag-based configuration does not support the design security or decompression features. table 10?1. configuration schemes for stratix iv devices (part 2 of 2) configuration scheme msel2 msel1 msel0 table 10?2. uncompressed raw binary file (.rbf) sizes for stratix iv devices device data size (bits) ep4se230 94,557,472 ep4se360 128,395,584 ep4se530 171,722,064 ep4se820 241,684,472 ep4sgx70 47,833,352 ep4sgx110 47,833,352 ep4sgx180 94,557,472 ep4sgx230 94,557,472 ep4sgx290 128,395,584 171,722,064 (1) ep4sgx360 128,395,584 171,722,064 (1) ep4sgx530 171,722,064 ep4s40g2 94,557,472 ep4s40g5 171,722,064 ep4s100g2 94,557,472 ep4s100g3 171,722,064 ep4s100g4 171,722,064 ep4s100g5 171,722,064 note to table 10?2 : (1) this only applies to the f45 package. 10?4 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices configuration features stratix iv device handbook september 2012 altera corporation volume 1 f for more information about setting device configuration options or creating configuration files, refer to the device configuration options and configuration file formats chapters in volume 2 of the configuration handbook . configuration features stratix iv devices offer design security, decompression, and remote system upgrade features. design security using configuration bitstream encryption is available in stratix iv devices, which protects your designs. stratix iv devices can receive a compressed configuration bitstream and decomp ress this data in real-time, reducing storage requirements and configuration time. you can make real-time system upgrades from remote locations of your st ratix iv designs with the remote system upgrade feature. table 10?3 lists which configuration features you can use in each configuration scheme. you can also refer to the following: for more information about the configuratio n data decompression feature, refer to ?configuration data decompression? on page 10?47 . for more information about the remote system upgrade feature, refer to ?remote system upgrades? on page 10?49 . for more information about the desi gn security feature, refer to ?design security? on page 10?63 . if your system already contains a common flash interface (cfi) flash memory, you can use it for stratix iv device configuration storage as well. the ma x ii parallel flash loader (pfl) feature in max ii devices provides an efficient method to program cfi flash memory devices through the jtag inte rface and provides the logic to control configuration from the flash memory device to the stratix iv device. both ps and fpp configuration modes are supported using this pfl feature. f for more information about pfl, refer to parallel flash loader megafunction user guide . for more information about programming altera serial configuration devices, refer to ?programming serial configur ation devices? on page 10?22 . table 10?3. configuration features for stratix iv devices configuration scheme configuration method decompression design security remote system upgrade fpp max ii device or a microprocessor with flash memory y (1) y (1) y fast as serial configuration device y y y ps max ii device or a microprocessor with flash memory y y ? download cable y y ? jtag max ii device or a microprocessor with flash memory ? ? ? download cable ? ? ? note to table 10?3 : (1) in these modes, the host system must send a dclk that is 4 the data rate. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?5 configuration features september 2012 altera corporation stratix iv device handbook volume 1 power-on reset circuit the por circuit keeps the entire system in reset until the power supply voltage levels have stabilized on power-up. after power-up, the device does not release nstatus until v cc , v ccaux , v ccpt , v ccpgm , and v ccpd are above the device?s por trip point. on power down, brown-out occurs if the v cc , v ccaux , v ccpt , v ccpgm , or v ccpd drops below the threshold voltage. in stratix iv devices, a pin-selectable option ( porsel) is provided that allows you to select between the standard por time or fast por time. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms, which has a lower power-ramp rate. when porsel is driven high, the fast por time is 4 ms < t por < 12 ms. v ccpgm pins stratix iv devices have a power supply, v ccpgm , for all the dedicated configuration pins and dual function pins. the supported co nfiguration voltage is 1.8, 2.5, and 3.0 v. stratix iv devices do not support 1.5 v configuration. use the v ccpgm pin to power all dedicated configuration inputs, dedicated configuration outputs, dedica ted configuration bidirectional pins, and some of the dual functional pins that you use for configuration. with v ccpgm , the configuration input buffers do not have to share power lines with the regular i/o buffer in stratix iv devices. the operating voltage for the configuration input pin is independent of the i/o banks power supply v ccio during configuration. therefore, stratix iv devices do not need configuration voltage constraints on v ccio . v ccpd pins stratix iv devices have a dedicated programming power supply, v ccpd , which must be connected to 3.0 v/2.5 v to power the i/o pre-drivers and jtag i/o pins ( tck , tms , tdi , tdo , and trst ). 1 v ccpgm and v ccpd must ramp up from 0 v to the desired voltage level within 100 ms when porsel is low or 4 ms when porsel is high. if these supplies are not ramped up within this specified time, your stratix iv device will not config ure successfully. if your system cannot ramp up the power supplies within 100 ms or 4 ms, you must hold nconfig low until all the power supplies are stable. 1 v ccpd must be greater than or equal to v ccio of the same bank. if v ccio of the bank is set to 3.0 v, v ccpd must be powered up to 3.0 v. if the v ccio of the bank is powered to 2.5 v or lower, v ccpd must be powered up to 2.5 v. for more information about configuration pins power supply, refer to ?device configuration pins? on page 10?39 . 10?6 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast passive parallel configuration stratix iv device handbook september 2012 altera corporation volume 1 fast passive parallel configuration fast passive parallel configuration in stra tix iv devices is designed to meet the continuously increasing demand for faster configuration times. stratix iv devices are designed with the capability of receivin g byte-wide configuration data per clock cycle. you can perform fpp configuration of stratix iv devices using an intelligent host, such as a max ii device or a microprocessor. fpp configuration using a max ii device as an external host fpp configuration using an external host provides the fastest method to configure stratix iv devices. in this configuration scheme, you can use a max ii device as an intelligent host that controls the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. you can store configuration data in .rbf , .hex , or .ttf format. when using the max ii device as an intelligent host, a design that controls the configuration proces s, such as fetching the data from flash memory and sending it to the device, mu st be stored in the max ii device. 1 if you are using the stratix iv decompression and/or design security features, the external host must be able to send a dclk frequency that is 4 the data rate. the 4 dclk signal does not require an addi tional pin and is sent on the dclk pin. the maximum dclk frequency is 125 mhz, which resu lts in a maximum data rate of 250 mbps. if you are not using the stratix iv decompression or design security features, the data rate is 8 the dclk frequency. figure 10?1 shows the configuration interface connections between the stratix iv device and a max ii device for single device configuration. figure 10?1. single device fpp configuration using an external host note to figure 10?1 : (1) connect the resistor to a supply that provides an acceptable input signal fo r the stratix iv device. v ccpgm must be high enough to meet the v ih specification of the i/o on the device and the external host. alte ra recommends powering up all configuration system i/os with v ccpgm. (2) a pull-up or pull-down resi stor helps keep the nconfig line in a known st ate when the external host is not driving the line. external host (max ii de v ice or microprocessor) co n f_do n e nstatus nce data[7..0] nco n fig stratix i v de v ice memory addr data[7..0] g n d msel[2..0] v ccpgm (1) v ccpgm/ v ccio (2) v ccpgm (1) g n d dclk nceo n .c. 10 k 10 k 10 k chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?7 fast passive parallel configuration september 2012 altera corporation stratix iv device handbook volume 1 after power-up, the stratix iv device goes through a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?9 fast passive parallel configuration september 2012 altera corporation stratix iv device handbook volume 1 1 if you need to stop dclk , it can only be stopped: three clock cycles after the last data by te was latched into the stratix iv device when you use the decompression and/or design security features. two clock cycles after the last data byte was latched into the stratix iv device when you do not use the stratix iv decompression and/or design security features. by stopping dclk , the configuration circuit allows en ough clock cycles to process the last byte of latched configuration data. when the clock restarts, the max ii device must provide data on the data[7..0] pins prior to sending the first dclk rising edge. if an error occurs during config uration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device and pin options dialog box) is turned on, the device releases nstatus after a reset time-out period (a maximum of 500 ? s). after nstatus is released and pulled high by a pull-up resistor, the max ii device can try to reconfigure the targ et device without needing to pulse nconfig low. if this option is turned off, the max ii de vice must generate a low-to-high transition (with a low pulse of at least 2 ? s) on nconfig to restart the configuration process. 1 if you have enabled the auto-restart config uration after error option, the nstatus pin transitions from high to low and back agai n to high when a configuration error is detected. this appears as a low pulse at the nstatus pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the ma x ii device must monitor the conf_done pin to detect errors and determine when programming completes. if all the configuration data is sent, but the conf_done or init_done signals have not gone high, the max ii device reconfigures the target device. 1 if you use the optional clkusr pin and nconfig is pulled low to restart the configuration during device initialization, ensure that clkusr continues toggling during the time nstatus is low (a maximum of 500 ? s). when the device is in user mode, initiating reconfiguration is done by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 ? s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. after nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. 10?10 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast passive parallel configuration stratix iv device handbook september 2012 altera corporation volume 1 figure 10?2 shows how to configure multiple stratix iv devices using a max ii device. this circuit is similar to the fpp configuration circuit for a single device, except the devices are cascaded for multi-device configuration. in a multi-device fpp configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the first device completes configuration in a multi-device config uration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins configuration within one clock cycle; therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in th e chain. the configuration signals may require buffering to ensure signal integrit y and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices init ialize and enter user mode at the same time. all nstatus and conf_done pins are tied together; if any device detects an error, configuration stops for the entire chain and you must reconfigure the entire chain. for example, if the first de vice flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart configuration after error option is turned on, the devices release their nstatus pins after a reset time-out period (a maximum of 500 ? s). after all nstatus pins are released and pulled high, th e max ii device tries to reconfigure the chain without pulsing nconfig low. if this option is turned off, the max ii device must generate a low-to-high transiti on (with a low pulse of at least 2 ? s) on nconfig to restart the configuration process. figure 10?2. multi-device fpp configuration using an external host note to figure 10?2 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for al l stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o standard on the device and the extern al host. altera recommends powe ring up all configuration system i/os with v ccpgm. (2) a pull-up or pull-down resist or helps keep the nconfig line in a known state wh en the external host is not driving the line. co n f_do n e nstatus nce data[7..0] nco n fig stratix i v de v ice 1 stratix i v de v ice 2 memory addr data[7..0] g n d v ccpgm (1) v ccpgm (1) dclk nceo co n f_do n e nstatus nce data[7..0] nco n fig dclk nceo n .c. 10 k 10 k external host (max ii de v ice or microprocessor) msel[2..0] g n d msel[2..0] g n d v ccpgm/ v ccio (2) 10 k chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?11 fast passive parallel configuration september 2012 altera corporation stratix iv device handbook volume 1 1 if you have enabled the auto-restart config uration after error option, the nstatus pin transitions from high to low and back agai n to high when a configuration error is detected. this appears as a low pulse at the nstatus pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. in a multi-device fpp configuration chain, all stratix iv devices in the chain must either enable or disable the decompression and/or design security features. you cannot selectively enable the decompression and/or design security features for each device in the chain because of the data and dclk relationship. if the chain contains devices that do not support design secu rity, use a serial configuration scheme. if a system has multiple devices that contain the same configuration data, tie all device nce inputs to gnd and leave the nceo pins floating. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. configuration signal s may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices mu st be the same density and package. all devices start and complete configuration at the same time. figure 10?3 shows a multi-device fpp configuration when both stratix iv devices are receiving the same configuration data. you can use a single configuration chain to configure stratix iv devices with other altera devices that support fpp configuration, such as other types of stratix devices. to ensure that all devices in the chain comple te configuration at the same time, or that an error flagged by one device initiates reco nfiguration in all devices, tie all of the device conf_done and nstatus pins together. f for more information about configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains in volume 2 of the configuration handbook. figure 10?3. multiple-device fpp configuration using an external host when both devices receive the same data notes to figure 10?3 : (1) connect the resistor to a supply that provides an acceptable input sign al for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on th e device and the external host. altera recommend s powering up all configuration system i/os with v ccpgm. (2) a pull-up or pull-down resist or helps keep the nconfig line in a known state wh en the external host is not driving the line. (3) the nceo pins of both stratix iv devi ces are left unconnected when c onfiguring the same configurati on data into multiple devices. co n f_do n e nstatus nce data[7..0] nco n fig stratix i v de v ice stratix i v de v ice memory addr data[7..0] v ccpgm (1) v ccpgm (1) dclk nceo n .c. (3) co n f_do n e nstatus nce data[7..0] nco n fig g n d dclk nceo n .c. 10 k 10 k external host (max ii de v ice or microprocessor) g n d msel[2..0] msel[2..0] g n d g n d v ccpgm/ v ccio (2) 10 k 10?12 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast passive parallel configuration stratix iv device handbook september 2012 altera corporation volume 1 fpp configuration timing figure 10?4 shows the timing waveform for an fpp configuration when using a max ii device as an external host. this waveform shows the timing when you have not enabled the decompression and design security features. table 10?4 lists the timing parameters for strati x iv devices for an fpp configuration when you have not enabled the decompression and design security features. figure 10?4. fpp configuration timing waveform (note 1) , (2) notes to figure 10?4 : (1) use this timing waveform when you have not en abled the decompression a nd design security features. (2) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reco nfiguration cycle begins. (3) after power-up, the st ratix iv device holds nstatus low for the time of the por delay. (4) after power-up, before and during configuration, conf_done is low. (5) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (6) data[7..0] are available as user i/o pins after configuration except for some exceptions on stratix iv gt devi ces. the state of these pins depends on the dual-purpose pin settings. nco n fig nstatus (3) co n f_do n e (4) dclk data[7..0] user i/o i n it_do n e byte 0 byte 1 byte 2 byte 3 byte n-2 byte n-1 byte n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (6) (5) user mode table 10?4. fpp timing parameters for stratix iv devices (part 1 of 2) (note 1) , (2) symbol parameter minimum maximum units stratix iv (7) stratix iv (8) stratix iv (9) stratix iv (7) stratix iv (8) stratix iv (9) t cf2cd nconfig low to conf_done low ? 800 ns t cf2st0 nconfig low to nstatus low ? 800 ns t cfg nconfig low pulse width 2 ? ? s t status nstatus low pulse width 10 500 (3) ? s t cf2st1 nconfig high to nstatus high ? 500 (4) ? s t cf2ck nconfig high to first rising edge on dclk 500 ? ? s chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?13 fast passive parallel configuration september 2012 altera corporation stratix iv device handbook volume 1 t st2ck nstatus high to first rising edge of dclk 2? ? s t dsu data setup time before rising edge on dclk 4 ? ns t dh data hold time after rising edge on dclk 1?ns t r input rise time ? 40 ns t input fall time ? 40 ns t cd2um conf_done high to user mode (5) 55 150 ? s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ?? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (8532 clkusr period) ?? t ch dclk high time (6) 3.6 4.5 5.6 ? ns t cl dclk low time (6) 3.6 4.5 5.6 ? ns t clk dclk period (6) 8 10 12.5 ? ns f max dclk frequency ? 125 100 80 mhz notes to table 10?4 : (1) this information is preliminary. (2) use these timing parameters when you have not enabled the decompression and design security features. (3) you can obtain this value if you do not delay the configuration by extending the nconfig or nstatus low pulse width. (4) this value is applicable if you do not delay the configuration by externally holding nstatus low. (5) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for starting the device. (6) adding up t ch and t cl equals to t clk . when ep4se230 t ch is 3.6 ns (min), t cl must be 4.4 ns and vice versa. (7) applicable to ep4se230, ep4s e360, ep4sgx70, ep4sgx110, ep4s gx180, ep4sgx230, ep4sgx290 (except f45 package), ep4sgx360 (exce pt f45 package), ep4s40g2, ep4s100g2 devices. (8) applicable to ep4se530, ep4sgx290 (only for f45 package), ep4s gx360 (only for f45 package), ep4sgx530, ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5 devices. (9) applicable to ep4se820 only. table 10?4. fpp timing parameters for stratix iv devices (part 2 of 2) (note 1) , (2) symbol parameter minimum maximum units stratix iv (7) stratix iv (8) stratix iv (9) stratix iv (7) stratix iv (8) stratix iv (9) 10?14 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast passive parallel configuration stratix iv device handbook september 2012 altera corporation volume 1 figure 10?5 shows the timing waveform for an fpp configuration when using a max ii device as an external host. this waveform shows the timing when you have enabled the decompression and/or design security features. table 10?5 lists the timing parameters for strati x iv devices for an fpp configuration when you enable the decompression and/or the design security features. figure 10?5. fpp configuration timing waveform with decompression or design security feature enabled (note 1) , (2) notes to figure 10?5 : (1) use this timing waveform when yo u have enabled the decompression and/or design security features. (2) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reco nfiguration cycle begins. (3) after power-up, the st ratix iv device holds nstatus low for the time of the por delay. (4) after power-up, before and during configuration, conf_done is low. (5) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (6) data[7..0] are available as user i/o pins after configuration except for some exceptions on stratix iv gt d evices. the state of these pins depends on the dual-purpose pin settings. (7) if needed, you can pause dclk by holding it low. when dclk restarts, the external host must provide data on the data[7..0] pins prior to sending the first dclk rising edge. nco n fig nstatus (3) co n f_do n e (4) dclk data[7..0] user i/o i n it_do n e t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck high-z user mode 12341234 1 byte 0 byte 1 byte 2 byte (n-1) byte n 4 3 t dsu t dh status t dh t ch t cl t clk (7) (5) (6) user mode table 10?5. fpp timing parameters for stratix iv devices with the decompression and/or design security features enabled (note 1) , (2) (part 1 of 2) symbol parameter minimum maximum units stratix iv (7) stratix iv (8) stratix iv (9) stratix iv (7) stratix iv (8) stratix iv (9) t cf2cd nconfig low to conf_done low ? 800 ns t cf2st0 nconfig low to nstatus low ? 800 ns t cfg nconfig low pulse width 2 ? ? s t status nstatus low pulse width 10 500 (3) ? s t cf2st1 nconfig high to nstatus high ? 500 (4) ? s t cf2ck nconfig high to first rising edge on dclk 500 ? ? s chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?15 fast passive parallel configuration september 2012 altera corporation stratix iv device handbook volume 1 f for more information about device configuration options and how to create configuration files, refer to the device configuration options and configuration file formats chapters in volume 2 of the configuration handbook . t st2ck nstatus high to first rising edge of dclk 2? ? s t dsu data setup time before rising edge on dclk 4?ns t dh data hold time after rising edge on dclk 3/( dclk frequency) + 1 ? s t data data rate ? 250 mbps t r input rise time ? 40 ns t input fall time ? 40 ns t cd2um conf_done high to user mode (5) 55 150 ? s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ?? t cd2umc conf_done high to user mode with clkusr option on (5) t cd2cu + (8532 clkusr period) ? ? t ch dclk high time (6) 3.6 4.5 5.6 ? ns t cl dclk low time (6) 3.6 4.5 5.6 ? ns t clk dclk period (6) 8 10 12.5 ? ns f max dclk frequency ? 125 100 80 mhz notes to table 10?5 : (1) this information is preliminary. (2) use these timing parameters when you use the decompression and/ or design security features. (3) you can obtain this value if you do not delay the configuration by extending the nconfig or nstatus low pulse width. (4) this value is applicable if you do not delay the configuration by externally holding nstatus low. (5) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for starting the device. (6) adding up t ch and t cl equals to t clk . when ep4se230 t ch is 3.6 ns (min), t cl must be 4.4 ns and vice versa. (7) applicable for ep4se230, ep4s e360, ep4sgx70, ep4sgx110, ep4s gx180, ep4sgx230, ep4sgx290 (excep t f45 package), ep4sgx360 (exc ept f45 package), ep4s40g2, ep4s100g2 devices. (8) applicable for ep4se530, ep4sgx290 (onl y for f45 package), ep4sgx360 (only for f45 package), ep4sgx 530, ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5 devices. (9) applicable to ep4se820 only. table 10?5. fpp timing parameters for stratix iv devices with the decompression and/or design security features enabled (note 1) , (2) (part 2 of 2) symbol parameter minimum maximum units stratix iv (7) stratix iv (8) stratix iv (9) stratix iv (7) stratix iv (8) stratix iv (9) 10?16 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast active serial configurati on (serial configuration devices) stratix iv device handbook september 2012 altera corporation volume 1 fpp configuration us ing a microprocessor in this configuration scheme, a microprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. all information in ?fpp configuration using a max ii device as an external host? on page 10?6 is also applicable when using a micr oprocessor as an external host. refer to this section for all configuration and timing information. fast active serial configuration (serial configuration devices) in the fast as configuration scheme, strati x iv devices are configured using a serial configuration device. these configuratio n devices are low-cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor. the largest serial configuration device currently supports 128 mbits of configuration bitstream. use the stratix iv decompressio n features or select an fpp or ps configuration scheme for ep 4se360, ep4sgx290, ep4s40g5, ep4s100g3 and larger devices. f for more information about serial co nfiguration devices, refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . serial configuration devices provide a seri al interface to access configuration data. during device configuration, stratix iv devices read configuration data using the serial interface, decompress data if necess ary, and configure their sram cells. this scheme is referred to as the as configur ation scheme because th e stratix iv device controls the configuration interface. this scheme contrasts with the ps configuration scheme where the configuration device controls the interface. 1 the stratix iv decompression and design se curity features are fully available when configuring your stratix iv device using fast as mode. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?17 fast active serial configuration (serial configuration devices) september 2012 altera corporation stratix iv device handbook volume 1 serial configuration device s have a four-pin interface?serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active-low chip select ( ncs ). this four-pin interface connects to stra tix iv device pins, as shown in figure 10?6 . you can power the epcs serial configuratio n device with 3.0 v when you configure the stratix iv fpga using active serial (as) configuration mode. this is feasible because the power supply to the epcs device ranges between 2.7 v and 3.6 v. you do not need a dedicated 3.3 v power supply to power the epcs device . the epcs device and the vccpgm pins on the stratix iv device may share the same 3.0 v power supply. after power-up, the stratix iv devices go through a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?19 fast active serial configuration (serial configuration devices) september 2012 altera corporation stratix iv device handbook volume 1 1 if you have enabled the auto-restart config uration after error option, the nstatus pin transitions from high to low and back agai n to high when a configuration error is detected. this appears as a low pulse at the nstatus pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. when the stratix iv device is in user mode , you can initiate reconfiguration by pulling the nconfig pin low. the nconfig pin must be low for at least 2 ? s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. after nconfig returns to a logic high level and nstatus is released by the stratix iv device, reconfiguration begins. 1 if you wish to gain control of the epcs pins, hold the nconfig pin low and pull the nce pin high. this causes the device to rese t and tri-state the as configuration pins. the timing parameters for as mode are not listed here because the t cf2cd , t cf2st0 , t cfg , t status , t cf2st1 , and t cd2um timing parameters are identical to the timing parameters for ps mode listed in table 10?7 on page 10?30 . you can configure multiple stratix iv devices using a single serial configuration device. you can cascade multiple strati x iv devices using the chip-enable ( nce ) and chip-enable-out ( nceo ) pins. the first device in the chain must have its nce pin connected to gnd. yo u must connect its nceo pin to the nce pin of the next device in the chain. when the first device captures all of its configuration data from the bitstream, it drives the nceo pin low, enabling the next device in the chain. you must leave the nceo pin of the last de vice unconnected. the nconfig , nstatus , conf_done , dclk , and data0 pins of each device in the chain are connected (refer to figure 10?7 ). the first stratix iv device in the chain is the configuration master and controls configuration of the entire chain. you must connect its msel pins to select the as configuration scheme. the remaining stratix iv devices are config uration slaves. you must connect their msel pins to select the ps config uration scheme. any other altera device that supports ps configuration can also be part of the chain as a configuration slave. 10?20 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast active serial configurati on (serial configuration devices) stratix iv device handbook september 2012 altera corporation volume 1 figure 10?7 shows the pin connections for the mu lti-device fast as configuration. as shown in figure 10?7 , the nstatus and conf_done pins on all target devices are connected together with external pull-up resistors. these pins are open-drain bidirectional pins on the devices. when the first device asserts nceo (after receiving all of its configuration data), it releases its conf_done pin. but the subsequent devices in the chain keep this shared conf_done line low until they have received their configuration data. when all target devi ces in the chain have received their configuration data and have released conf_done , the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. if an error occurs at any po int during configuration, the nstatus line is driven low by the failing device. if you enable the auto-restart configuration after error option, reconfiguration of the entire chain begins after a reset time -out period (a maximum of 500 ? s). if you did not enable the auto-restart configuration after error option, the external system must monitor nstatus for errors and then pulse nconfig low to restart configuration. the external system can pulse nconfig if it is under system control rather than tied to v ccgpm . 1 if you have enabled the auto-restart config uration after error option, the nstatus pin transitions from high to low and back agai n to high when a configuration error is detected. this appears as a low pulse at the nstatus pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. figure 10?7. multi-device fast as configuration notes to figure 10?7 : (1) connect the pull-up resistors to v ccpgm at a 3.0-v supply. (2) connect the repeater buffers between the stratix iv master and slave device(s) for data[0] and dclk . this is to preven t potential signal integrity and clock skew problems. data dclk ncs asdi data0 dclk ncso asdo serial config u ration de v ice stratix i v de v ice master stratix i v de v ice sla v e 10 k 10 k g n d nceo nce nstatus co n f_do n e data0 dclk nceo nce nstatus co n f_do n e 10 k nco n fig nco n fig n .c. msel1 msel0 g n d msel2 v ccpgm msel1 msel0 msel2 g n d v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm (1) b u ffers (2) chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?21 fast active serial configuration (serial configuration devices) september 2012 altera corporation stratix iv device handbook volume 1 1 while you can cascade stratix iv devices, yo u cannot cascade or chain together serial configuration devices. if the configuration bitstream size exceed s the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. when configuring multiple devices, the size of the bitstream is the sum of the individual device configuration bitstreams. a system may have multiple devices that contain the same configuration data. in active serial chains, you can implement this by storing one copy of the .sof in the serial configuration device . the same copy of the .sof configures the master stratix iv device and all remaining slave devices concur rently. all stratix iv devices must be the same density and package. to configure four identical stra tix iv devices with the same .sof , set up the chain as shown in figure 10?8 . the first device is the master device and its msel pins must be set to select as configuration. the other th ree slave devices are set up for concurrent configuration and their msel pins must be set to select ps configuration. the nce input pins from the master and slave are connected to gnd, and the data and dclk pins connect in parallel to all four devices. during the configuration cycle, the master device reads its configuration data from th e serial configuration device and transmits the configuration data to all three sl ave devices, configuring all of them simultaneously. 10?22 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast active serial configurati on (serial configuration devices) stratix iv device handbook september 2012 altera corporation volume 1 figure 10?8 shows the multi-device fast as co nfiguration when the devices receive the same data using a single .sof . estimating active seri al configuration time active serial configuration time is dominated by the time it takes to transfer data from the serial configuration device to the stratix iv device. this serial interface is clocked by the stratix iv dclk output (generated from an internal oscillator) and must be set to 40 mhz (25 ns) .therefore, the minimum configuratio n time estimate for an ep4se230 device (94, 600, 000 bits of uncompressed data) is: rbf size (minimum dclk period / 1 bit per dclk cycle) = esti mated minimum configuration time 94, 600, 000 bits (25 ns / 1 bit) = 2365 ms enabling compression reduces the amount of configuration data that is transmitted to the stratix iv device, which also reduces configuration time. on average, compression reduces configuration time, depending on the design. figure 10?8. multi-device fast as configuration when the devices receive the same data using a single .sof notes to figure 10?8 : (1) connect the pull-up resistors to v ccpgm at a 3.0-v supply. (2) connect the repeater buffers between the stratix iv master and slave device(s) for data[0] and dclk . this is to prevent potential signal integrity and clock skew problems. data dclk ncs asdi data0 dclk ncso asdo serial config u ration de v ice stratix i v de v ice master 10 k 10 k g n d nceo nce nstatus co n f_do n e data0 dclk nceo nce nstatus co n f_do n e 10 k nco n fig nco n fig n .c. msel1 msel0 msel2 msel1 msel0 g n d msel2 v ccpgm data0 dclk stratix i v de v ice sla v e stratix i v de v ice sla v e stratix i v de v ice sla v e nceo nce nstatus co n f_do n e nco n fig n .c. msel1 msel0 g n d msel2 v ccpgm data0 dclk nceo nce nstatus co n f_do n e nco n fig n .c. msel1 msel0 g n d msel2 v ccpgm g n d v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm (1) b u ffers (2) g n d n .c. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?23 fast active serial configuration (serial configuration devices) september 2012 altera corporation stratix iv device handbook volume 1 programming serial co nfiguration devices serial configuration devices are non-volati le, flash-memory-based devices. you can program these devices in-system using th e usb-blaster?, ethernetblaster?, or byteblaster? ii download cable. alternatively, you can program them using the altera programming unit (apu), supported third- party programmers, or a microprocessor with the srunner software driver. you can perform in-system programming of serial configuration devices using the conventional as programming interfac e or the jtag interface solution. because serial conf iguration devices do not suppo rt the jtag interface, the conventional method to program them is using the as programming interface. the configuration data used to program serial configuration devices is downloaded using programming hardware. during in-system programming, the download cable disables device access to the as interface by driving the nce pin high. stratix iv devices ar e also held in reset by a low level on nconfig . after programming is complete, the download cable releases nce and nconfig , allowing the pull-down and pull-up resistors to drive gnd and v ccpgm , respectively. figure 10?9 shows the download cable connections for the serial configuration device. altera has developed serial flashloader (sfl), an in-system programming solution for serial configuration devices using the jtag interface. this solution requires the stratix iv device to be a bridge betw een the jtag interface and the serial configuration device. f for more information about sfl, refer to an 370: using the serial flashloader with quartus ii software . 10?24 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fast active serial configurati on (serial configuration devices) stratix iv device handbook september 2012 altera corporation volume 1 f for more information about the usb-bl aster download cable, refer to the usb-blaster download cable user guide . for more information about the byteblaster ii cable, refer to the byteblaster ii downl oad cable user guide . for more information about the ethernetblaster download cable, refer to the ethernetblaster communications cable user guide. you can program serial configuration device s with the quartus ii software using the altera programming hardware and th e appropriate configuration device programming adapter. in production environments, you can prog ram serial configuration devices using multiple methods. you can use altera pr ogramming hardware or other third-party programming hardware to program blank seri al configuration devices before they are mounted on pcbs. alternatively, you can use an on-board microprocessor to program the serial configuration device in-system using c-based software drivers provided by altera. figure 10?9. in-system programming of serial configuration devices notes to figure 10?9 : (1) connect these pull-up resistors to v ccpgm at a 3.0-v supply. (2) power up the usb-byteblaster, bytebl aster ii, or ethernetblaster cable?s v cc(trgt) with v ccpgm . data dclk ncs asdi data0 dclk ncso nce nco n fig nstatus nceo co n f_do n e asdo v ccpgm 10 k 10 k 10 k 10 k stratix i v de v ice serial config u ration de v ice pin 1 usb blaster or byteblaser ii (as mode) 10-pin male header n .c. (2) msel1 msel0 g n d msel2 v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm (1) chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?25 passive serial configuration september 2012 altera corporation stratix iv device handbook volume 1 you can program a serial configuratio n device in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming, which can be easily customized to fit in different embedded systems. srunner is able to read raw programming data (. rpd ) and write to serial configuration devi ces. the serial co nfiguration device programming time using srunner is compar able to the programming time with the quartus ii software. f for more information about srunner, refer to an 418: srunner: an embedded solution for serial configuration device programming and the source code on the altera website at www.altera.com . f for more information about programming seri al configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . guidelines for connecting serial conf iguration devices on an as interface for single- and multi-device as configurati ons, the board trace length and loading between the supported serial configuration device and the stratix iv device family must follow the recommendations listed in table 10?6 . passive serial configuration you can program a ps configuration for stratix iv devices using an intelligent host, such as a max ii device or microprocessor with flash memory, or a download cable. in the ps scheme, an external host (a max i i device, embedded processor, or host pc) controls configuration. configuration data is clocked into the target stratix iv device using the data0 pin at each rising edge of dclk . 1 the stratix iv decompression and design se curity features are fully available when configuring your stratix iv device using ps mode. table 10?6. maximum trace length and loading for the as configuration stratix iv device as pins maximum board trace length from the stratix iv device to the serial configuration device (inches) maximum board load (pf) dclk 10 15 data[0] 10 30 ncso 10 30 asdo 10 30 10?26 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices passive serial configuration stratix iv device handbook september 2012 altera corporation volume 1 ps configuration using a max i i device as an external host in this configuration scheme, you can use a max ii device as an intelligent host that controls the transfer of configuration da ta from a storage device, such as flash memory, to the target stratix iv device. you can store configuration data in .rbf , .hex , or .ttf format. figure 10?10 shows the configuration interface connections between a stratix iv device and a max ii device for single device configuration. after power-up, stratix iv devices go thro ugh a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms 10?28 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices passive serial configuration stratix iv device handbook september 2012 altera corporation volume 1 initialization is complete, the init_done pin is released and pulled high. the max ii device must be able to detect this low-to -high transition that signals the device has entered user mode. when initialization is co mplete, the device enters user mode. in user-mode, the user i/o pins no longer ha ve weak pull-up resistors and function as assigned in your design. 1 two dclk falling edges are required after conf_done goes high to begin the initialization of the device for both unco mpressed and compressed bitstream in ps. to ensure dclk and data0 are not left floating at the end of configuration, the max ii device must drive them either high or low, whichever is convenient on your board. the data[0] pin is available as a user i/o pin af ter configuration. when you chose the ps scheme as a default in the quartus ii software, this i/o pin is tri-stated in user mode and must be driven by the max ii device. to change this default option in the quartus ii software, select the dual-purpose pins tab of the device and pin options dialog box. the configuration clock ( dclk ) speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists, which means you can pause the configuration by halting dclk for an indefinite amount of time. if an error occurs during config uration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device and pin options dialog box) is turned on, the stratix iv device releases nstatus after a reset time-out period (a maximum of 500 ? s). after nstatus is released and pulled high by a pull-up resistor, the max ii device can try to reconfigure th e target device without needing to pulse nconfig low. if this option is turned of f, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 ? s) on nconfig to restart the configuration process. 1 if you have enabled the auto-restart config uration after error option, the nstatus pin transitions from high to low and back agai n to high when a configuration error is detected. this appears as a low pulse at the nstatus pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the conf_done pin must be monitored by the max ii device to detect errors and determine when prog ramming completes. if all configuration data is sent, but conf_done or init_done have not gone high, the max ii device must reconfigure the target device. 1 if you use the optional clkusr pin and nconfig is pulled low to restart configuration during device initialization, you must ensure that clkusr continues toggling during the time nstatus is low (a maximum of 500 ? s). when the device is in user-mode, you can initiate a reconfiguration by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 ? s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. after nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?29 passive serial configuration september 2012 altera corporation stratix iv device handbook volume 1 figure 10?11 shows how to configure multiple devices using a max ii device. this circuit is similar to the ps configuration circ uit for a single device, except the stratix iv devices are cascaded for mu lti-device configuration. in multi-device ps configuration, the first device?s nce pin is connected to gnd, while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the first device completes configuration in a mu lti-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins configuration within one clock cycle. therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrit y and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices init ialize and enter user mode at the same time. because all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and you must reconfigure the entire chain. for example, if the fi rst device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart configuration after error option is turned on, the devices release their nstatus pins after a reset time-out period (a maximum of 500 ? s). after all nstatus pins are released and pulled high, the max ii device can try to reconfigure the chain without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a lo w pulse of at least 2 ? s) on nconfig to restart the configuration process. figure 10?11. multi-device ps configuration using an external host note to figure 10?11 : (1) connect the resistor to a supply that provides an acceptable input sign al for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on the device an d the external host. altera recommends powering up all configuration system i/os with v ccpgm . (2) a pull-up or pull-down resist or helps keep the nconfig line in a known state wh en the external host is not driving the line. co n f_do n e nstatus nce data 0 nco n fig stratix i v de v ice 1 stratix i v de v ice 2 memory addr data0 g n d 10 k 10 k dclk co n f_do n e nstatus nce data0 nco n fig dclk nceo nceo n .c. external host (max ii de v ice or microprocessor) msel1 msel0 g n d msel2 v ccpgm msel1 msel0 g n d msel2 v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm/ v ccio (2) 10 k 10?30 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices passive serial configuration stratix iv device handbook september 2012 altera corporation volume 1 1 if you have enabled the auto-restart config uration after error option, the nstatus pin transitions from high to low and back agai n to high when a configuration error is detected. this appears as a low pulse at the nstatus pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. in your system, you can have multiple de vices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while the nceo pins are left floating. al l other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices start and complete configuration at the same time. figure 10?12 shows multi-device ps configuration when both stratix iv devices are receiving the same configuration data. you can use a single configuration chain to configure stratix iv devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. f for more information about configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . figure 10?12. multiple-device ps configuration when both devices receive the same data notes to figure 10?12 : (1) connect the resistor to a supply that provides an acceptable input sign al for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on the device an d the external host. altera recommends powering up all configuration system i/os with v ccpgm . (2) a pull-up or pull-down resist or helps keep the nconfig line in a known state wh en the external host is not driving the line. (3) the nceo pins of both devices are le ft unconnected when co nfiguring the same configuration data into multiple devices. co n f_do n e nstatus nce data 0 nco n fig stratix i v de v ice stratix i v de v ice memory addr data0 g n d 10 k 10 k dclk co n f_do n e nstatus nce data0 nco n fig dclk nceo nceo n .c. external host (max ii de v ice or microprocessor) msel1 msel0 g n d msel2 v ccpgm msel1 msel0 g n d msel2 v ccpgm n .c. g n d (3) (3) v ccpgm (1) v ccpgm (1) v ccpgm/ v ccio (2) 10 k chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?31 passive serial configuration september 2012 altera corporation stratix iv device handbook volume 1 ps configuration timing figure 10?13 shows the timing waveform for ps configuration when using a max ii device as an external host. table 10?7 lists the timing parameters for stra tix iv devices for ps configuration. figure 10?13. ps configuration timing waveform (note 1) notes to figure 10?13 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reco nfiguration cycle begins. (2) after power-up, the st ratix iv device holds nstatus low for the time of the por delay. (3) after power-up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) data[0] is available as a user i/o pin after configuration. the st ate of this pin depends on th e dual-purpose pin settings. nco n fig nstatus (2) co n f_do n e (3) dclk data user i/o i n it_do n e bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (4) table 10?7. ps timing parameters for stratix iv devices (part 1 of 2) (note 1) symbol parameter minimum maximum units t cf2cd nconfig low to conf_done low ? 800 ns t cf2st0 nconfig low to nstatus low ? 800 ns t cfg nconfig low pulse width 2 ? ? s t status nstatus low pulse width 10 500 (2) ? s t cf2st1 nconfig high to nstatus high ? 500 (3) ? s t cf2ck nconfig high to first rising edge on dclk 500 ? ? s t st2ck nstatus high to first rising edge of dclk 2? ? s t dsu data setup time before rising edge on dclk 4?ns t dh data hold time after rising edge on dclk 0?ns t ch dclk high time (5) 3.2 ? ns t cl dclk low time (5) 3.2 ? ns t clk dclk period (5) 8?ns f max dclk frequency ? 125 mhz t r input rise time ? 40 ns 10?32 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices passive serial configuration stratix iv device handbook september 2012 altera corporation volume 1 f device configuration options and how to cr eate configuration files are described in the device configuration options and configuration file formats chapters in volume 2 of the configuration handbook . ps configuration using a microprocessor in this ps configuration scheme, a micr oprocessor controls the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. for more information about configuratio n and timing information, refer to ?ps configuration using a max ii device as an external host? on page 10?25 . this section is also applicable when using a microprocessor as an external host. ps configuration using a download cable 1 in this section, the generic term ?downloa d cable? includes the altera usb-blaster universal serial bus (usb) port download cable, masterblaster serial/usb communications cable, bytebl aster ii parallel port download cable, byteblastermv parallel port download cable, an d ethernetblaster download cable. in a ps configuration with a download cable, an intelligent host (such as a pc) transfers data from a storage device to the device using the usb blaster, masterblaster, byteblaster ii, ethernetblaster, or byteblastermv cable. after power-up, stratix iv devices go thro ugh a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms 10?34 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices passive serial configuration stratix iv device handbook september 2012 altera corporation volume 1 you can use a download cable to configure multiple stratix iv devices by connecting each device?s nceo pin to the subsequent device?s nce pin. the first device?s nce pin is connected to gnd, while its nceo pin is connected to the nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. all othe r configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. because all conf_done pins are tied together, all devices in the chain initia lize and enter user mode at the same time. in addition, because the nstatus pins are tied together, the entire chain halts configuration if any device detects an error. the auto-restart configuration after error option does not affect the configuratio n cycle because you mu st manually restart the configuration in the quartus ii software when an error occurs. figure 10?15 shows how to configure multiple stratix iv devices with a download cable. figure 10?15. multi-device ps configuration using a usb blas ter, ethernetblaster, masterblaster, byteblaster ii, or byteblastermv cable notes to figure 10?15 : (1) connect the pull-up resistor to the same supply voltage (v ccpgm ) as the usb blaster, masterblaster ( vio pin), byteblaster ii, byteblastermv, or ethernetblaster cable. (2) you only need the pull-up resistors on data0 and dclk if the download cable is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after configuration. for example, if you are also using a configuration device, you do not need the pull-up resistors on data0 and dclk . (3) pin 6 of the header is a v io reference voltage for the mast erblaster output driver. v io must match the device?s v ccpgm . for more information about this value, refer to the masterblaster serial/usb comm unications cable user guide . in the usb-blaster, byteblast er ii, and byteblastermv cables, this pin is a no connect. stratix iv device 1 stratix iv device 2 nce nconfig conf_done dclk nce nconfig conf_done dclk nceo gnd (ps mode) v ccpgm (1) nstatus nstatus data0 data0 gnd 10 k 10 k 10 k 10 k 10 k pin 1 download cable 10-pin male header nceo n.c. gnd v io (3 ) (2) (2) msel1 msel0 gnd msel2 msel1 msel0 gnd msel2 v ccpgm (1) v ccpgm (1) v ccpgm (1) v ccpgm (1) v ccpgm (1) v ccpgm (1 ) v ccpgm (1) chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?35 jtag configuration september 2012 altera corporation stratix iv device handbook volume 1 f for more information about how to use the us b blaster, masterblaster, byteblaster ii, or byteblastermv cables, refer to the following user guides: usb-blaster download cable user guide masterblaster serial/usb commu nications cable user guide byteblaster ii download cable user guide byteblastermv download cable user guide ethernetblaster communications cable user guide jtag configuration jtag has developed a specification for boundary-scan testing. this boundary-scan test (bst) architecture offers the capability to efficiently test components on pcbs with tight lead spacing. the bst architecture can test pin connections without using physical test probes and capt ure functional data while a device is operating normally. you can also use jtag circuitry to shift configuration data into the device. the quartus ii software automatically generates .sof s that you can use for jtag configuration with a download cable in the quartus ii software programmer. f for more information about jtag boundary-scan testing and commands available using stratix iv devices, refer to the following documents: jtag boundary scan testin g in stratix iv devices chapter programming support for jam stapl language stratix iv devices are designed such that jtag instructions have precedence over any device configuration modes. therefore, jt ag configuration can take place without waiting for other configuration modes to complete. for example, if you attempt jtag configuration of stratix iv devices during ps configurat ion, ps configuration is terminated and jtag configuration begins. 1 you cannot use the stratix iv decompression or design security features if you are configuring your stratix iv device when using jtag-based configuration. 1 a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have weak internal pull-up resistors (typically 25 k ? ). the jtag output pin tdo and all jtag input pins are powered by 2.5-v/3.0-v v ccpd . all the jtag pins only support the lvttl i/o standard. all user i/o pins are tri-stat ed during jtag configuration. f all the jtag pins are powered by the v ccpd power supply of i/o bank 1a. for more information about how to connect a jtag chain with multiple voltages across the devices in the chain, refer to the jtag boundary scan testin g in stratix iv devices chapter . 10?36 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices jtag configuration stratix iv device handbook september 2012 altera corporation volume 1 during jtag configuration, you can download data to the device on the pcb through the usb blaster, masterblaster, byteblaster ii, ethernetblaster, or byteblastermv download cable. configuring devices thro ugh a cable is similar to programming devices in-system, except you must connect the trst pin to v ccpd . this ensures that the tap controller is not reset. figure 10?16 shows jtag configuration of a sing le stratix iv device when using a download cable. figure 10?16. jtag configuration of a single device using a download cable notes to figure 10?16 : (1) connect the pull-up resistor to the same supply voltage as the usb blaster, masterblaster ( vio pin), byteblaster ii, byteblastermv, or ethernetblaster cable. the voltage su pply can be connected to the v ccpd of the device. (2) connect the nconfig and msel[2..0] pins to support a non-jtag configuration scheme. if you only use the jtag configuration, connect nconfig to v ccpgm and msel[2..0] to gnd. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the mast erblaster output driver. v io must match the device?s v ccpd . for more information about this value, refer to the masterblaster serial/usb commun ications cable user guide . in the usb-blaster, byteblaste r ii, and byteblastermv cable, this pin is a no connect. (4) you must connect nce to gnd or driven low for successful jtag configuration. (5) the pull-up resistor valu e can vary from 1 k to 10 k ? . nce (4) msel[2..0] nco n fig co n f_do n e v ccpd (1) g n d g n d (2) (2) v ccpd (1) 10 k 10 k nstatus pi n 1 dow n load cable 10-pi n male heade r (jtag mode) (top view) g n d tck tdo tms tdi 1 k g n d v io (3) stratix i v de v ice nce0 n .c. trst dclk (2) v ccpgm v ccpgm v ccpd (1) v ccpd (1) (5) (5) chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?37 jtag configuration september 2012 altera corporation stratix iv device handbook volume 1 to configure a single device in a jtag ch ain, the programming software places all other devices in bypass mode. in bypass mode, devices pass programming data from the tdi pin to the tdo pin through a single bypass re gister without being affected internally. this scheme enables the progra mming software to program or verify the target device. configuration data driven into the device appears on the tdo pin one clock cycle later. the quartus ii software verifies successful jtag configuration upon completion. at the end of configuration, the software checks the state of conf_done through the jtag port. when the quartus ii software generates a jam file (. jam) for a multi-device chain, it contains instructions so that all the devices in th e chain are initialized at the same time. if conf_done is not high, the quartus ii software indicates that configuration has failed. if conf_done is high, the software indicates that configuration was successful. after the configuration bitstream is transmitted serially using the jtag tdi port, the tck port is clocked an addition al 1,094 cycles to perform device initialization. stratix iv devices have dedicated jtag pins that always function as jtag pins. not only can you perform jtag testing on strati x iv devices before and after, but also during configuration. while ot her device families do not support jtag testing during configuration, stratix iv devices support th e bypass, id code, and sample instructions during configuration without interrupting co nfiguration. all other jtag instructions may only be issued by first interrupting configuration and reprogramming the i/o pins using the config_io instruction. the config_io instruction allows i/o buffers to be configured using the jtag port and when issued, interrupts configuration. this instruction allows you to perform board-level testing prior to configuring the stratix iv device or waiting for a configuration device to complete config uration. after configuration has been interrupted and jtag testing is complete, you must reconfigure the part using jtag ( pulse_config instruction) or by pulsing nconfig low. the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on stratix iv devices do not affect jtag bo undary-scan or programming operations. toggling these pins does not affect jt ag operations (other than the usual boundary-scan operation). when designing a board for jtag configuration for stratix iv devices, consider the dedicated configuration pins. table 10?8 lists how these pins are connected during jtag configuration. table 10?8. dedicated configuration pin connections during jtag configuration (part 1 of 2) signal description nce on all stratix iv devices in the chain, nce must be driven low by connecting it to gnd, pulling it low using a resistor, or driving it by some control circuitry. for devices that are also in multi-device fpp, as, or ps configuration chains, the nce pins must be connected to gnd during jtag configuration or jtag must be configured in the same order as the configuration chain. nceo on all stratix iv devices in the chain, you can leave nceo floating or connected to the nce of the next device. msel do not leave these pins floating. these pins support whichever non-jtag configuration is used in production. if you only use jtag configuration, tie these pins to gnd. 10?38 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices jtag configuration stratix iv device handbook september 2012 altera corporation volume 1 when programming a jtag device chain, one jtag-compatible header is connected to several devices. the number of devices in the jtag chain is limited only by the drive capability of the download cable. when four or more devices are connected in a jtag chain, altera recommends buffering the tck , tdi , and tms pins with an on-board buffer. jtag-chain device programming is ideal when the system contains multiple devices, or when testing your system using jtag bst circuitry. figure 10?17 shows a multi-device jtag configuration when using a download cable. nconfig driven high by connecting to v ccpgm , pulling up using a resistor, or driven high by some control circuitry. nstatus pull to v ccpgm using a 10-k ?? resistor. when configuring multiple devices in the same jtag chain, each nstatus pin must be pulled up to v ccpgm individually. conf_done pull to v ccpgm using a 10-k ?? resistor. when configuring multiple devices in the same jtag chain, each conf_done pin must be pulled up to v ccpgm individually. conf_done going high at the end of jtag configuration indicates successful configuration. dclk do not leave dclk floating. drive low or high, whichever is more convenient on your board. table 10?8. dedicated configuration pin connections during jtag configuration (part 2 of 2) signal description figure 10?17. jtag configuration of multiple devices using a download cable notes to figure 10?17 : (1) connect the pull-up resistor to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii, byteblastermv, or ethernetblaster cable. connect the voltage supply to v ccpd of the device. (2) connect the nconfig and msel[2..0] pins to support a non-jtag configuration scheme. if you only use a jtag configuration, connect nconfig to v ccpgm and msel[2..0] to gnd. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the m asterblaster output driver. v io must match the device?s v ccpd . for more information about this value, refer to the masterblaster serial/usb comm unications cable user guide . in the usb-blaster, byteblaster ii, and byteblastermv cables, this pin is a no connect. (4) you must connect nce to gnd or drive it low for successful jtag configuration. (5) the pull-up resistor valu e can vary from 1 k to 10 k ? . tms tck dow n load cable 10-pi n male heade r (jtag mode) tdi tdo v ccpd v ccpd (1) pi n 1 nstatus nco n fig msel[2..0] nce (4) v ccpgm co n f_do n e tms tck tdi tdo nstatus nco n fig msel[2..0] nce (4) co n f_do n e tms tck tdi tdo nstatus nco n fig msel[2..0] nce (4) co n f_do n e (1) (2) (2) (2) (2) (2) (2) v io (3) stratix i v de v ice stratix i v de v ice stratix ii or stratix ii gx de v ice trst trst trst 10 k 10 k 10 k 10 k 10 k 1 k 10 k dclk dclk dclk (2) (2) (2) stratix i v de v ice v ccpd (1) v ccpd (1) v ccpd (1) v ccpd (1) v ccpgm v ccpgm v ccpgm v ccpgm v ccpgm (5) (5) chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?39 jtag configuration september 2012 altera corporation stratix iv device handbook volume 1 you must connect the nce pin to gnd or drive it low during jtag configuration. in multi-device fpp, as, and ps configu ration chains, th e first device?s nce pin is connected to gnd, while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. in addition, the conf_done and nstatus signals are all shared in multi-device fpp, as, or ps configuration ch ains so the devices can enter user mode at the same time after configuration is complete. when the conf_done and nstatus signals are shared among all the devices, you must configure every device when jtag configuration is performed. if you only use jtag configuration, alte ra recommends connecting the circuitry as shown in figure 10?17 , where each of the conf_done and nstatus signals are isolated, so that each device can enter user mode individually. after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. theref ore, if these devices are also in a jtag chain, ensure the nce pins are connected to gnd during jtag configuration or that the devices are jtag configured in the same order as the configuration chain. as long as the devices are jtag configured in the same order as the multi-device configuration chain, the nceo of the previous device drives the nce of the next device low when it has successfully been jtag configured. you can place other altera devices that have jtag support in the same jtag chain for device programming and configuration. 1 jtag configuration support is enhanced and al lows more than 17 stratix iv devices to be cascaded in a jtag chain. f for more information about configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . you can configure stratix iv devices using multiple configuration schemes on the same board. combining jtag configuration with as configuration on your board is useful in the prototyping environment because it allows multiple methods to configure your fpga. f for more information about combining jtag configuration with other configuration schemes, refer to the combining different configuration schemes chapter in volume 2 of the configuration handbook . 10?40 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices device configuration pins stratix iv device handbook september 2012 altera corporation volume 1 figure 10?18 shows jtag configuration of a stra tix iv device using a microprocessor. jam stapl jam ? stapl, jedec standard jesd-71, is a standard file format for in-system programmability (isp) purposes. jam stap l supports programming or configuration of programmable devices and testing of el ectronic systems, using the ieee 1149.1 jtag interface. jam stapl is a freely licensed open standard. the jam player provides an interface for ma nipulating the ieee std. 1149.1 jtag tap state machine. f for more information about jtag and jam stapl in embedded environments, refer to using jam stapl for isp via an embedded processor . to download the jam player, visit the altera website at www.altera.com . device configuration pins the following tables list the connections and functionality of all the configuration-related pins on stratix iv devices. table 10?9 lists the stratix iv configuration pins an d their power supply. figure 10?18. jtag configuration of a single device using a microprocessor notes to figure 10?18 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for all st ratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of th e i/o on the device. (2) connect the nconfig and msel[2..0] pins to support a non-jtag configuration scheme. if you use only a jtag configuration, connect nconfig to v ccgpm and msel[2..0] to gnd. pull dclk either high or low, whichever is convenient on your board. (3) connect nce to gnd or drive it low for successful jtag configuration. (4) the microprocessor must u se the same i/o standard as v ccpd to drive the jtag pins. trst tdi (4) tck (4) tms (4) tdo (4) microprocessor memory addr data stratix iv device nstatus conf_done v ccpgm (1) 10 k 10 k (3) nce nconfig n.c. gnd (2) (2) v ccpd nceo msel[2..0] dclk (2) v ccpgm (1) table 10?9. stratix iv configuration pin summary (part 1 of 2) (note 1) description input/output dedicated powered by configuration mode tdi input yes v ccpd jtag tms input yes v ccpd jtag tck input yes v ccpd jtag trst input yes v ccpd jtag tdo output yes v ccpd jtag crc_error output ? pull-up optional, all modes chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?41 device configuration pins september 2012 altera corporation stratix iv device handbook volume 1 data0 input ? v ccpgm /v ccio (3) all modes except jtag data[7..1] input ? v ccpgm/ v ccio (3) fpp init_done output ? pull-up optional, all modes clkusr input ? v ccpgm /v ccio (3) optional nstatus bidirectional yes v ccpgm /pull-up all modes nce input yes v ccpgm all modes conf_done bidirectional yes v ccpgm /pull-up all modes nconfig input yes v ccpgm all modes porsel input yes v cc (2) all modes asdo (4) output yes v ccpgm as ncso (4) output yes v ccpgm as dclk (4) input yes v ccpgm ps, fpp output yes v ccpgm as nio_pullup input yes v cc (2) all modes nceo output yes v ccpgm all modes msel[2..0] input yes v cc (2) all modes notes to table 10?9 : (1) the total number of pins is 29. the total number of dedicated pins is 18. (2) although msel[2..0], porsel, and nio_pullup are powered up by v cc , altera recommends conn ecting these pins to v ccpgm or gnd directly without using a pull-up or pull-down resistor. (3) these pins are powered up by v ccpgm during configuration. these pins are powered up by v ccio if they are used as regular i/o in user mode. (4) to tri-state this pin, in the quartus ii software, on the assignments menu, select device . on the device page, select device and pin options... on the device and pin options page, select configuration and select the enable input tri-state on active configuration pins in user mode option. table 10?9. stratix iv configuration pin summary (part 2 of 2) (note 1) description input/output dedicated powered by configuration mode 10?42 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices device configuration pins stratix iv device handbook september 2012 altera corporation volume 1 table 10?10 lists the dedicated configuration pins. you must connect these pins properly on your board for successful configuration. some of these pins may not be required for your configuration schemes. table 10?10. dedicated configuration pins on the stratix iv device (part 1 of 4) pin name user mode configuration scheme pin type description vccpgm n/a all power dedicated power pin. use this pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bidirectional pins, and some of the dual functional pins that are used for configuration. you must connect this pin to 1.8, 2.5, or 3.0 v. v ccpgm must ramp-up from 0 v to v ccpgm within 100 ms when porsel is low or 4 ms when porsel is high. if v ccpgm is not ramped up within this specified time, your stratix iv device will not configure successfully. if your system does not allow a v ccpgm ramp-up within 100 ms or 4 ms, you must hold nconfig low until all power supplies are stable. vccpd n/a all power dedicated power pin. use this pin to power the i/o pre-drivers, jtag input and output pins, and design security circuitry. you must connect this pin to 2.5 v or 3.0 v, depending on the i/o standards selected. for the 3.0-v i/o standard, v ccpd = 3.0 v. for the 2.5 v or below i/o standards, v ccpd =2.5v. v ccpd must ramp-up from 0 v to 2.5 v / 3.0 v within 100 ms when porsel is low or 4 ms when porsel is high. if v ccpd is not ramped up within this specified time, your stratix iv device will not configure successfully. if your system does not allow a v ccpd to ramp-up time within 100 ms or 4 ms, you must hold nconfig low until all power supplies are stable. porsel n/a all input dedicated input that selects between a standard por time or a fast por time. a logic low selects a standard por time setting of 100 ms < t por < 300 ms and a logic high selects a fast por time setting of 4 ms < t por < 12 ms. the porsel input buffer is powered by v cc and has an internal 5-k ?? pull-down resistor that is always active. tie the porsel pin directly to v ccpgm or gnd. nio_pullup n/a all input dedicated input that chooses whether the internal pull-up resistors on the user i/o pins and dual-purpose i/o pins ( ncso , nasdo , data[7..0] , clkusr , and init_done ) are on or off before and during configuration. a logic high turns off the weak internal pull-up resistors; a logic low turns them on. the nio-pullup input buffer is powered by v cc and has an internal 5-k ? pull-down resistor that is always active. the nio-pullup can be tied directly to v ccpgm , using a 1-k ? pull-up resistor or tied directly to gnd, depending on your device requirements. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?43 device configuration pins september 2012 altera corporation stratix iv device handbook volume 1 msel[2..0] n/a all input three-bit configuration input that sets the stratix iv device configuration scheme. for the appropriate connections, refer to table 10?1 on page 10?2 . you must hardwire these pins to v ccpgm or gnd. the msel[2..0] pins have internal 5-k ? pull-down resistors that are always active. nconfig n/a all input configuration control input. pulling this pin low during user-mode causes the device to lose its configuration data, enter a reset state, and tri-stat e all i/o pins. returning this pin to a logic high level initiates a reconfiguration. configuration is possible only if this pin is high, except in jtag programming mode, when nconfig is ignored. nstatus n/a all bidirectional open-drain the device drives nstatus low immediately after power-up and releases it after the por time. during user mode and regular configuration, this pin is pulled high by an external 10-k ? resistor. this pin, when driven low by the stratix iv device, indicates that the device has encountered an error during configuration. status output?if an error occurs during configuration, nstatus is pulled low by the target device. status input?if an external source drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if you use a configuration device, driving nstatus low causes the configuration device to attempt to configure the device, but because the device ignores transitions on nstatus in user mode, the device does not reconfigure. to initiate a reconfiguration, nconfig must be pulled low. if you have enabled the auto-restart configuration after error option, the nstatus pin transitions from high to low and back again to high when a configuration error is detected. this appears as a low pulse at the pin with a minimum pulse width of 10 ? s to a maximum pulse width of 500 ? s, as defined in the t status specification. table 10?10. dedicated configuration pins on the stratix iv device (part 2 of 4) pin name user mode configuration scheme pin type description 10?44 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices device configuration pins stratix iv device handbook september 2012 altera corporation volume 1 nstatus (continued) ?? ? if v ccpgm is not fully powered up, the following could occur: v ccpgm is powered high enough for the nstatus buffer to function properly and nstatus is driven low. when v ccpgm is ramped up, por trips and nstatus is released after por expires. v ccpgm is not powered high enough for the nstatus buffer to function properly. in this situation, nstatus might appear logic high, triggering a configuration attempt that would fail because por did not yet trip. when v ccpd is powered up, nstatus is pulled low because por did not yet trip. when por trips after v ccpgm is powered up, nstatus is released and pulled high. at that point, reconfiguration is triggered and the device is configured. conf_done n/a all bidirectional open-drain status output. the target device drives the conf_done pin low before and during configuration. after all the configuration data is received without error and the initialization cycle starts, the target device releases conf_done . status input. after all the data is received and conf_done goes high, the target device initializes and enters user mode. the conf_done pin must have an external 10-k ? pull-up resistor for the device to initialize. driving conf_done low after configuration and initialization does not affect the configured device. nce n/a all input active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, it must be tied low. in multi-device configuration, nce of the first device is tied low, while its nceo pin is connected to nce of the next device in the chain. the nce pin must also be held low for successful jtag programming of the device. nceo n/a all output output that drives low when device configuration is complete. in single device configuration, this pin is left floating. in multi-device configuration, this pin feeds the next device?s nce pin. the nceo of the last device in the chain is left floating. the nceo pin is powered by v ccpgm . asdo n/a as output control signal from the stratix iv device to the serial configuration device in as mode used to read out configuration data. in as mode, asdo has an internal pull-up resistor that is always active. table 10?10. dedicated configuration pins on the stratix iv device (part 3 of 4) pin name user mode configuration scheme pin type description chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?45 device configuration pins september 2012 altera corporation stratix iv device handbook volume 1 ncso n/a as output output control signal from the stratix iv device to the serial configuration device in as mode that enables the configuration device. in as mode, ncso has an internal pull-up resistor that is always active. dclk n/a synchronous configuration schemes (ps, fpp, as) input (ps, fpp) output (as) in ps and fpp configurations, dclk is the clock input used to clock data from an external source into the target device. data is latched into the device on the rising edge of dclk . in as mode, dclk is an output from the stratix iv device that provides timing for the configuration interface. in as mode, dclk has an internal pull-up resistor (typically 25 k ? ) that is always active. in as configuration schemes, this pin is driven into an inactive state after configuration completes. you can use this pin as a user i/o during user mode. in ps or fpp schemes that use a control host, you must drive dclk either high or low, whichever is more convenient. in passive schemes, you cannot use dclk as a user i/o during user mode. toggling this pin after configuration does not affect the configured device. data0 n/a in as mode. i/o in ps or fpp mode. ps, fpp, as input data input. in serial configuration modes, bit-wide configuration data is presented to the target device on the data0 pin. in as mode, data0 has an internal pull-up resistor that is always active. after ps or fpp configuration, data0 is available as a user i/o pin. the state of this pin depends on the dual-purpose pin settings. data[7..1] i/o parallel configuration schemes (fpp) inputs data inputs. byte-wide configuration data is presented to the target device on data[7..0] . in serial configuration schemes, they function as user i/o pins during configuration, which means they are tri-stated. after fpp configuration, data[7..1] are available as user i/o pins. the state of these pins depends on the dual-purpose pin settings. table 10?10. dedicated configuration pins on the stratix iv device (part 4 of 4) pin name user mode configuration scheme pin type description 10?46 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices device configuration pins stratix iv device handbook september 2012 altera corporation volume 1 table 10?11 lists the optional configuration pins. if these optional configuration pins are not enabled in the quartus ii software, th ey are available as general-purpose user i/o pins. therefore, during configuration, these pins function as user i/o pins and are tri-stated with we ak pull-up resistors. table 10?11. optional configuration pins pin name user mode pin type description clkusr n/a if option is on. i/o if option is off. input optional user-supplied clock input synchronizes the initialization of one or more devices. enable this pin by turning on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software. init_done n/a if option is on. i/o if option is off. output open-drain use as a status pin to indicate when the device has initialized and is in user mode. when nconfig is low and during the beginning of configuration, the init_done pin is tri-stated and pulled high due to an external 10-k ? pull-up resistor. after the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high and the device enters user mode. thus, the monitoring circuitry must be able to detect a low-to-high transition. enable this pin by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if option is on. i/o if option is off. input optional pin that allows you to override all tri-states on the device. when this pin is driven low, all i/o pins are tri-stated. when this pin is driven high, all i/o pins behave as programmed. enable this pin by turning on the enable device-wide output enable ( dev_oe ) option in the quartus ii software. dev_clrn n/a if option is on. i/o if option is off. input optional pin that allows you to override all clears on all device registers. when this pin is driven low, all registers are cleared. when this pin is driven high, all registers behave as programmed. enable this pin by turning on the enable device-wide reset ( dev_clrn ) option in the quartus ii software. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?47 device configuration pins september 2012 altera corporation stratix iv device handbook volume 1 table 10?12 lists the dedicated jtag pins. jtag pi ns must be kept stable before and during configuration to prevent accident al loading of jtag instructions. the tdi , tms, and trst pins have weak internal pull-up resistors, while tck has a weak internal pull-down resistor (typically 25 k ? ). if you plan to use the signaltap ? embedded logic array analyzer, you must connect the jtag pins of the stratix iv device to a jtag header on your board. f for more information about the pin connection recommendations, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . table 10?12. dedicated jtag pins pin name user mode pin type description tdi n/a test data input serial input pin for instructions as well as test and programming data. data is shifted on the rising edge of tck . the tdi pin is powered by the 2.5-v/3.0-v v ccpd supply. if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting this pin to logic high using a 1-k ? resistor. tdo n/a test data output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. the tdo pin is powered by v ccpd . for recommendations about connecting a jtag chain with multiple voltages across the devices in the chain, refer to the jtag boundary scan testing in stratix iv devices chapter. if the jtag interface is not required on your board, you can disable the jtag circuitry by leaving this pin unconnected. tms n/a test mode select input pin that provides the control signal to determine the transitions of the tap controller state machine. tms is evaluated on the rising edge of tck . therefore, you must set up tms before the rising edge of tck . transitions within the state machine occur on the falling edge of tck after the signal is applied to tms . the tms pin is powered by 2.5-v/3.0-v v ccpd . if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting this pin to logic high using a 1-k ? resistor. tck n/a test clock input clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. the tck pin is powered by the 2.5-v/3.0-v v ccpd supply. it is expected that the clock input waveform have a nominal 50% duty cycle. if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting tck to gnd. trst n/a test reset input (optional) active-low input to asynchronously reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149.1. the trst pin is powered by the 2.5-v/3.0-v v ccpd supply. hold tms at 1 or keep tck static while trst is changed from 0 to 1. if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting the trst pin to gnd. 10?48 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices configuration data decompression stratix iv device handbook september 2012 altera corporation volume 1 configuration data decompression stratix iv devices support configuration data decompression, which saves configuration memory space and time. this feature allows you to store compressed configuration data in configuration devi ces or other memory and transmit this compressed bitstream to stratix iv device s. during configurat ion, the stratix iv device decompresses the bitstream in re al time and programs its sram cells. 1 preliminary data indicates that compress ion typically reduces the configuration bitstream size by 30% to 55% based on the designs used. stratix iv devices support decompression in the fpp (when using a max ii device or microprocessor + flash), fast as, and ps configuration schemes. the stratix iv decompression feature is not availabl e in the jtag configuration scheme. in ps mode, use the stratix iv decompre ssion feature because sending compressed configuration data reduces configuration time. when you enable compression, the quartus ii software generates configuration files with compressed configuration data. this compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time needed to transmit the bitstream to the stratix iv device. the time required by a stratix iv device to decompress a configurat ion file is less than the time needed to transmit the configuration data to the device. there are two ways to enable compression for stratix iv bitstreams?before design compilation (in the compiler settings menu) and after design compilation (in the convert programming files window). to enable compression in the project?s compiler settings menu, follow these steps: 1. on the assignments menu, click device to bring up the settings dialog box. 2. after selecting your stratix iv device, open the device and pin options window. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?49 configuration data decompression september 2012 altera corporation stratix iv device handbook volume 1 3. in the configuration settings tab, turn on generate compressed bitstreams (as shown in figure 10?19 ). you can also enable compression when creating programming files from the convert programming files window. to do this, follow these steps: 1. on the file menu, click convert programming files . 2. select the programming file type ( .pof , .sram , .hex , .rbf , or .ttf ). 3. for .pof output files, select a configuration device. 4. in the input files to convert box, select sof data . 5. select add file and add a stratix iv device .sof file. 6. select the name of the file you added to the sof data area and click properties . 7. check the compression check box. figure 10?19. enabling compression for stratix iv bitstreams in compiler settings 10?50 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote system upgrades stratix iv device handbook september 2012 altera corporation volume 1 when multiple stratix iv devices are ca scaded, you can selectively enable the compression feature for each device in the chain if you are using a serial configuration scheme. figure 10?20 shows a chain of two stratix i v devices. the first stratix iv device has compression enabled; therefore, receives a compressed bitstream from the configuration device. the se cond stratix iv device has the compression feature disabled and receives uncompressed data. in a multi-device fpp configuration chain (with a max ii device or microprocessor + flash), all stratix iv devices in the chai n must either enab le or disable the decompression feature. you cannot selectiv ely enable the compression feature for each device in the chain because of the data and dclk relationship. you can generate programming files for this setup by clicking convert programming files on the file menu in the quartus ii software. remote system upgrades this section describes the functionality an d implementation of the dedicated remote system upgrade circuitry. it also defines several concepts relate d to remote system upgrade, including factory configuration, application configuration, remote update mode, and user watchdog timer. additionally, this section provides design guidelines for implementing remote system upgrad es with the supported configuration schemes. system designers sometimes face challenges such as shortened design cycles, evolving standards, and system deployment s in remote locations. stratix iv devices help overcome these challenges with their inherent reprogrammability and dedicated circuitry to perform remote system upgrades. remote system upgrades help deliver feature enhancements and bug fixes without costly recalls, redu ce time-to-market, extend product life, and avoid system downtime. stratix iv devices feature dedicated remote sy stem upgrade circuitry. soft logic (either the nios ? ii embedded processor or user logic) implemented in a stratix iv device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circui try performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and pr ovides error status information. figure 10?20. compressed and uncompressed configurat ion data in the same configuration file nce g n d nceo decompression controller stratix i v de v ice nce nceo n .c. s e r ial co n fig ur atio n data comp r e ss ed u n comp r e ss ed co n fig ur atio n data co n fig ur atio n data serial config u ration de v ice stratix i v de v ice chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?51 remote system upgrades september 2012 altera corporation stratix iv device handbook volume 1 remote system upgrade is supported in fast as stratix iv configuration schemes. you can also implement remote system upgrade in conjunction with advanced stratix iv features such as real-time decompression of configuration data and design security using the advanced encryption standard (aes) for secure and efficient field upgrades. the largest serial configuration device currently supports 128 mbits of configuration bitstream. 1 stratix iv devices only support remote system upgrade in the single device fast as configuration scheme. because the largest serial configuratio n device currently supports 128 mbits of configuration bitstream, the remote system upgrade feature is not supported in ep4sgx290, ep4se360, and larger devices. 1 the remote system upgrade feature is not supported in a multi-device chain. functional description the dedicated remote system upgrade circui try in stratix iv devices manages remote configuration and provides error detection, recovery, and status information. user logic or a nios ii processor implemented in the stratix iv device logic array provides access to the remote configuration data source and an interface to the system?s configuration memory. stratix iv devices have remo te system upgrade processes that involve the following steps: 1. a nios ii processor (or user logic) implemented in the stratix iv device logic array receives new configuration data from a remote location. the connection to the remote source uses a communication protocol such as the transmission control protocol/internet protocol (tcp/ip), peri pheral component interconnect (pci), user datagram protocol (udp), univer sal asynchronous receiver/transmitter (uart), or a proprietary interface. 2. the nios ii processor (or user logic) stores this new configuration data in non-volatile configuration memory. 3. the nios ii processor (or user logic) initiates a reconfiguration cycle with the new or updated configuration data. 4. the dedicated remote system upgrade ci rcuitry detects and recovers from any error(s) that might occur du ring or after the reconfig uration cycle and provides error status information to the user design. 10?52 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote system upgrades stratix iv device handbook september 2012 altera corporation volume 1 figure 10?21 shows the steps required for performing remote configuration updates. (the numbers in figure 10?21 coincide with the steps just mentioned.) figure 10?22 shows a block diagram for implementi ng a remote system upgrade with the stratix iv fast as configuration scheme. you must set the mode select pins ( msel[2..0] ) to fast as mode to use remote system upgrade in your system. table 10?13 lists the msel pin settings for stratix iv devices in standard configuration mode and remote system upgrade mode. the following sections describe remote update of the remote system upgrade mode. for more information about standard config uration schemes supported in stratix iv devices, refer to ?configuration schemes? on page 10?2 . figure 10?21. functional diagram of stratix iv remote system upgrade figure 10?22. remote system upgrade block diagram for stratix iv fast as configuration scheme table 10?13. remote system upgrade modes in stratix iv devices configuration scheme msel[2..0] remote system upgrade mode fast as (40 mhz) 011 standard 011 remote update (1) note to table 10?13 : (1) all epcs densities are able to support dclk up to 40 mhz, but batches of epcs1 and epcs4 ma nufactured on 0.18- ? m process geometry can only support dclk up to 20 mhz. for more information, refer to the serial configuration devices (epcs1, e pcs4, epcs16, epcs6 4, and epcs12 8 ) data sheet chapter in volume 2 of the configuration handbook . de v elopment location memory stratix i v config u ration stratix i v de v ice control mod u le data data data config u ration 1 2 3 stratix i v de v ice serial config u ration de v ice n ios ii processor or user logic chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?53 remote system upgrades september 2012 altera corporation stratix iv device handbook volume 1 1 when using fast as mode, you must select remote update mode in the quartus ii software and insert the altremote_update megafunction to access the circuitry. for more information, refer to ?altremote_update megafunction? on page 10?62 . enabling remote update you can enable remote update for stratix iv devices in the quartus ii software before design compilation (in the compiler settings menu). in remote update mode, the auto-restart configuration after error option is always enabled. to enable remote update in the project?s compiler settings , in the quartus ii software, follow these steps: 1. on the assignment menu, click device . the settings dialog box appears. 2. click device and pin options . the device and pin options dialog box appears. 3. click the configuration tab. 4. from the configuration scheme list, select active serial (you can also use configuration device ) ( figure 10?23 ). 5. from the configuration mode list, select remote ( figure 10?23 ). 6. click ok . 7. in the settings dialog box, click ok . figure 10?23. enabling remote update for stratix iv devices in the compiler settings menu 10?54 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote system upgrade mode stratix iv device handbook september 2012 altera corporation volume 1 configuration image types when performing a remote system upgr ade, stratix iv device configuration bitstreams are classified as factory config uration images or application configuration images. an image, also referred to as a co nfiguration, is a design loaded into the stratix iv device that performs certain user-defined functions. each stratix iv device in your system requ ires one factory image or the addition of one or more application images. the factory im age is a user-defined fall-back, or safe configuration, and is responsible for administering remote updates in conjunction with the dedicated circuitry. application images implement user-defined functionality in the target stratix iv device. you may include the default application image functionality in the factory image. a remote system upgrade involves storing a new application configuration image or updating an existing one using the remo te communication interface. after an application configuration image is stored or updated remotely, the user design in the stratix iv device initiates a reconfigurat ion cycle with the new image. any errors during or after this cycle are detected by the dedicated remote system upgrade circuitry and cause the device to automaticall y revert to the factory image. the factory image then performs error processing an d recovery. the factory configuration is written to the serial configur ation device only once by the system manufacturer and must not be remotely updated. on the othe r hand, application configurations may be remotely updated in the system. both images can initiate system reconfiguration. remote system upgrade mode remote system upgrade has one mode of operation?remote update mode. remote update mode allows you to determine the functionality of your system after power-up and offers several features. remote update mode in remote update mode, stratix iv devices load the factory configuration image after power up. the user-defined factory conf iguration determines which application configuration is to be loaded and triggers a reconfiguration cycle. the factory configuration may also contain application logic. when used with serial configuration de vices, remote update mode allows an application configuration to start at any flash sector boundary. for example, this translates to a maximum of 128 sectors in the epcs64 device and 32 sectors in the epcs16 device, where the minimum size of each page is 512 kbits. altera recommends not using the same page in the serial configuration devices for two images. additionally, remote update mode features a user watchdog timer that determines the validity of an application configuration. when a stratix iv device is first powered up in remote update mode, it loads the factory configuration located at page zero (page registers pgm[23:0] = 24'b0 ). always store the factory configuration image for your system at page address zero. this corresponds to the start address location 0 000000 in the serial configuration device. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?55 remote system upgrade mode september 2012 altera corporation stratix iv device handbook volume 1 the factory image is user-designed and contains soft logic to: process any errors based on status information from the dedicated remote system upgrade circuitry communicate with the remote host and receive new application configurations and store this new configuration data in the local non-volatile memory device determine which application configuration is to be loaded into the stratix iv device enable or disable the user watchdog time r and load its time-out value (optional) instruct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle figure 10?24 shows the transitions between the factory and application configurations in remote update mode. after power up or a configuration error, the factory configuration logic is loaded automatically. the factory conf iguration also must specify whether to enable the user watchdog timer for the application configuration and if enabled, to include the timer setting information. the user watchdog timer ensures that th e application configuration is valid and functional. the timer must be continually reset within a specific amount of time during user mode operation of an applicat ion configuration. only valid application configurations contain the logic to reset the timer in user mode. this timer reset logic must be part of a user-designed hardware and/or software health monitoring signal that indicates error-free system operation. if the timer is not reset in a specific amount of time; for example, the user application configuration detects a functional problem or if the system hangs, the dedicated ci rcuitry updates the remote system upgrade status register, triggering the loading of the factory configuration. figure 10?24. transitions between configurations in remote update mode set control register and reconfigure set control register and reconfigure reload a different application application n configuration application 1 configuration factory configuration (page 0) configuration error configuration error power up configuration error reload a different application 10?56 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote system upgrade mode stratix iv device handbook september 2012 altera corporation volume 1 1 the user watchdog timer is automatically disabled for factory configurations. for more information about the user watchdog timer, refer to ?user watchdog timer? on page 10?61 . if there is an error while loading the application configuration, the cause of the reconfiguration is written by the dedicated circuitry to the remote system upgrade status register. actions that cause the remo te system upgrade status register to be written are: nstatus driven low externally internal crc error user watchdog timer time-out a configuration reset (logic array nconfig signal or external nconfig pin assertion to low) stratix iv devices automatically load the fa ctory configuration located at page address zero. this user-designed factory configurat ion can read the remote system upgrade status register to determine the reason for the reconfiguration. the factory configuration then takes appropriate error recovery steps and writes to the remote system upgrade control register to determin e the next application configuration to be loaded. when stratix iv devices successfully load the application configuration, they enter into user mode. in user mode, the soft logic (nios ii processor or state machine and the remote communication interface) assi sts the stratix iv device in determining when a remote system update is arriving. when a remote system update arrives, the soft logic receives the incoming data, writes it to the configuration memory device, and triggers the device to load the factor y configuration. the factory configuration reads the remote system upgrade status register and control register, determines the valid application configuration to load, writes the remote system upgrade control register accordingly, and initiates system reconfiguration. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?57 dedicated remote syst em upgrade circuitry september 2012 altera corporation stratix iv device handbook volume 1 dedicated remote system upgrade circuitry this section describes the implementation of the stratix iv remote system upgrade dedicated circuitry. the remote system upgrade circuitry is implemented in hard logic. this dedicated circuitr y interfaces to the user-defined factory and application configurations implemented in the stratix iv device logic array to provide the complete remote configuration solution. the remote system upgrade circuitry contains the remote system upgrade register s, a watchdog timer, and a state machine that controls those components. figure 10?25 shows the data path for the remote system upgrade block. figure 10?25. remote system upgrade circuit data path (note 1) note to figure 10?25 : (1) the ru_dout, ru_shiftnld, ru_captnupdt, ru_clk, ru_din, ru_nconfig , and ru_nrstimer signals are internally controlled by the altremote_update megafunction. logic array shift register stat u s register (sr) [4..0] control register [37..0] din capt u re do u t bit [4..0] logic array clko u t ru_shiftnld ru_captnupdt ru_clk ru_di n ru_nco n fig ru_nrstimer user w atchdog timer ru_dout capt u re clkin u pdate logic array capt u re din bit [37..0] do u t u pdate update register [37..0] time-o u t rsu state machine internal oscillator 10?58 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices dedicated remote system upgrade circuitry stratix iv device handbook september 2012 altera corporation volume 1 remote system upgrade registers the remote system upgrade block contains a series of registers that store the page addresses, watchdog timer sett ings, and status information. table 10?14 lists these registers. the remote system upgrade control and status registers are clocked by the 10-mhz internal oscillator (the same oscillator that controls the us er watchdog timer). however, the remote system upgrade shift and update registers are clocked by the user clock input ( ru_clk ). remote system upgrade control register the remote system upgrade control register stores the application configuration page address and user watchdog timer settings. the control register functionality depends on the remote system upgrade mode selection. in remote update mode, the control register page address bits are set to all zeros ( 24'b0 = 0000000 ) at power up to load the factory configuration. a factory config uration in remote update mode has write access to this register. figure 10?26 and table 10?15 specify the control register bit positions. in the figure, the numbers show the bit position of a se tting within a register. for example, bit number 25 is the enable bit for the watchdog timer. table 10?14. remote system upgrade registers register description shift register this register is accessible by the logic array and allows the update, status, and control registers to be written and sampled by user logic. control register this register contains the current page address, user watchdog timer settings, and one bit specifying whether the current configuration is a factory configuration or an application configuration. during a read operation in an application configuration, this register is read into the shift register. when a reconfiguration cycle is initiated, the contents of the update register are written into the control register. update register this register contains data similar to that in the control register. however, it can only be updated by the factory configuration by shifting data into the shift register and issuing an update operation. when a reconfiguration cycle is triggered by the factory configuration, the control register is updated with the contents of the update register. during a capture in a f actory configuration, this register is read into the shift register. status register this register is written to by the remote system upgrade circuitry on every reconfiguration to record the cause of the reconfiguration. this information is used by the factory configuration to determine the appropriate action following a reconfiguration. during a capture cycle, this register is read into the shift register. figure 10?26. remote system upgrade control register wd_timer[11..0] wd_en pgm[23..0] anf 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 .. 3 2 1 0 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?59 dedicated remote syst em upgrade circuitry september 2012 altera corporation stratix iv device handbook volume 1 the application-not-factory ( anf ) bit indicates whether th e current configuration loaded in the stratix iv device is the factory configuration or an application configuration. this bit is set low by the remote system upgrade circuitry when an error condition causes a fall-back to the factory configuration. when the anf bit is high, the control register access is limited to read operations. when the anf bit is low, the register allows write operations and disables the watchdog timer. in remote update mode, the factory configurati on design sets this bit high (1'b1) when updating the contents of the update regis ter with the application page address and watchdog timer settings. table 10?15 lists the remote system upgrade control register contents. remote system upgrade status register the remote system upgrade status regist er specifies the reconfiguration trigger condition. the various trigger and error conditions include: cyclic redundancy check (crc) erro r during application configuration nstatus assertion by an external device due to an error stratix iv device logic array triggered a reconfiguration cycle, possibly after downloading a new application configuration image external configuration reset ( nconfig ) assertion user watchdog timer time-out table 10?15. remote system upgrade control register contents control register bit remote system upgrade mode value (2) definition anf (1) remote update 1'b0 application not factory pgm[23..0] remote update 24'b0000000 as configuration start address ( stadd[23..0] ) wd_en remote update 1'b0 user watchdog timer enable bit wd_timer[11..0] remote update 12'b000000000000 user watchdog time-out value (most significant 12 bits of 29-bit count value: {wd_timer[11..0], 17'b0} ) notes to table 10?15 : (1) in remote update mode, the remote co nfiguration block does not update the anf bit automatically (you can update it manually). (2) this is the default value of the control register bit. 10?60 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices dedicated remote system upgrade circuitry stratix iv device handbook september 2012 altera corporation volume 1 figure 10?27 and table 10?16 specify the contents of the status register. the numbers in the figure show the bit positions within a 5-bit register. remote system upgrade state machine the remote system upgrade control and update registers have identical bit definitions, but serve different roles (refer to table 10?14 on page 10?57 ). while both registers can only be updated when the device is loaded with a factory configuration image, the update register writes are controll ed by the user logic; the control register writes are controlled by the remote system upgrade state machine. in factory configurations, the user logic sends the anf bit (set high), the page address, and the watchdog timer settings for the ne xt application configuration bit to the update register. when the logic array configuration reset ( ru_nconfig ) goes low, the remote system upgrade state machine update s the control register with the contents of the update register and initiates system reconfiguration from the new application page. 1 to ensure successful reconfiguration between the pages, assert the ru_nconfig signal for a minimum of 250 ns. this is equivalent to strobing the reco nfiguration input of the altremote_update megafunction high for a minimum of 250 ns. in the event of an error or reconfigurat ion trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (page zero or page one, based on the mode and error condition) by setting the control register accordingly. table 10?17 lists the contents of the control register after such an event occurs for all possible error or trigger conditions. figure 10?27. remote system upgrade status register wd 4 crc 0 nconfig 3 nstatus 1 core_nconfig 2 table 10?16. remote system upgrade status register contents status register bit definition por reset value crc (from the configuration) crc error caused reconfiguration 1 bit '0' nstatus nstatus caused reconfiguration 1 bit '0' core_nconfig (1) device logic array caused reconfiguration 1 bit '0' nconfig nconfig caused reconfiguration 1 bit '0' wd watchdog timer caused reconfiguration 1 bit '0' note to table 10?16 : (1) logic array reconfiguration forces the sys tem to load the application configuration data into the stratix iv device. this oc curs after the factory configuration specifies the appropriate application configur ation page address by updating the update register. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?61 dedicated remote syst em upgrade circuitry september 2012 altera corporation stratix iv device handbook volume 1 the remote system upgrade status regist er is updated by the dedicated error monitoring circuitry after an error conditio n but before the factory configuration is loaded. capture operations during factory configur ation access the contents of the update register. this feature is used by the user logic to verify that the page address and watchdog timer settings were written corr ectly. read operations in application configurations access the cont ents of the control register. this information is used by the user logic in the application configuration. table 10?17. control register contents after an error or reconfiguration trigger condition reconfiguration error/trigger control register setting remote update nconfig reset all bits are 0 nstatus error all bits are 0 core triggered reconfiguration update register crc error all bits are 0 wd time out all bits are 0 10?62 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices dedicated remote system upgrade circuitry stratix iv device handbook september 2012 altera corporation volume 1 user watchdog timer the user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. the system uses the timer to detect functional errors after an application configuration is successfully loaded into the stratix iv device. the user watchdog timer is a counter that counts down from the initial value loaded into the remote system upgrade control re gister by the factory configuration. the counter is 29 bits wide and has a maximum count value of 2 29 . when specifying the user watchdog timer value, specify only the most significant 12 bits. the granularity of the timer setting is 2 17 cycles. the cycle time is ba sed on the frequency of the 10-mhz internal oscillator. table 10?18 lists the operating range of the 10-mhz internal oscillator. the user watchdog timer begins counting after the application configuration enters device user mode. this timer must be periodically reloaded or reset by the application configuration before the timer expires by asserting ru_nrstimer . if the application configuration does not reload the user wa tchdog timer before the count expires, a time-out signal is generated by the remote system upgrade dedicated circuitry. the time-out signal tells the re mote system upgrade circuitr y to set the user watchdog timer status bit ( wd ) in the remote system upgrade status register and reconfigures the device by loading the factory configuration. 1 to allow remote system upgrade dedicated ci rcuitry to reset the watchdog timer, you must assert the ru_nrstimer signal active for a minimum of 250 ns. this is equivalent to strobing the reset_timer input of the altremote_update megafunction high for a minimum of 250 ns. the user watchdog timer is not enabled duri ng the configuration cycle of the device. errors during configuration are detected by the crc engine. also, the timer is disabled for factory configurations. function al errors should not exist in the factory configuration because it is stored and validated during production and is never updated remotely. 1 the user watchdog timer is disabled in factory configurations and during the configuration cycle of the application configuration. it is enabled after the application configuration enters user mode. table 10?18. 10-mhz internal oscillator specifications (note 1) minimum typical maximum units 4.3 5.3 10 mhz note to table 10?18 : (1) these values are preliminary. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?63 quartus ii software support september 2012 altera corporation stratix iv device handbook volume 1 quartus ii software support the quartus ii software provides the flexibil ity to include the remote system upgrade interface between the stratix iv device logic array and the dedicated circuitry, generate configuration files for production , and allows remote programming of the system configuration memory. the altremote_update megafunction is the implementation option in the quartus ii software that you use for the in terface between the remote system upgrade circuitry and the device logic array interface. using the megafunction block instead of creating your own logic saves design time and offers more efficient logic synthesis and device implementation. altremote_update megafunction the altremote_update megafunction provides a memory-like interface to the remote system upgrade circuitry and hand les the shift register read and write protocol in the stratix iv device logic. this implementation is suitable for designs that implement the factory configuration functions using a nios ii processor or user logic in the device. figure 10?28 shows the interface signals between the altremote_update megafunction and nios ii processor or user logic. f for more information about the altremote_update megafunction and the description of ports shown in figure 10?28 , refer to the remote update circuitry (altremote_update) mega function user guide . figure 10?28. interface signals between the altremo te_update megafunction and the nios ii processor nios ii processor or user logic read_param write_param param[2..0] data_in[23..0] reconfig reset_timer clock reset busy data_out[23..0] altremote_update 10?64 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices design security stratix iv device handbook september 2012 altera corporation volume 1 design security this section provides an overview of the design security feature and its implementation on stratix iv devices using the advanced encryption standard (aes). it also covers the new security mo des available in stratix iv devices. as stratix iv devices continue play a role in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect the designs from copying, reverse engineering, and tampering. stratix iv devices address these concerns with both volatile and no n-volatile security feature support. stratix iv devices have the ability to decrypt configuration bitstreams using the aes algorithm, an industry-standar d encryption algorithm that is fips-197 certified. stratix iv devices have a design security feature that utilizes a 256-bit security key. stratix iv devices store configuration data in sram configuration cells during device operation. because sram is volatile, the sram cells must be loaded with configuration data each time the device powers up. it is possible to intercept configuration data when it is being transmitted from the memory source (flash memory or a configuration device) to the device. the intercepted configuration data could then be used to configure another device. when using the stratix iv design security fe ature, the security key is stored in the stratix iv device. depending on the security mode, you can configure the stratix iv device using a configuration file that is encrypted with the same key, or for board testing, configured with a normal configuration file. the design security feature is available when configuring stratix iv devices using fpp configuration mode with an external host (such as a max ii device or microprocessor), or when using fast as or ps configuration schemes. the design security feature is also available in remote update with fast as configuration mode. the design security feature is not available when you are configuring your stratix iv device using jtag-based configuration. for more information, refer to ?supported configuration schemes? on page 10?67 . 1 when using a serial configuration scheme such as ps or fast as, configuration time is the same whether or not you enable the design security feature. if the fpp scheme is used with the design security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared with the configuration time of a stratix iv device that has neither the de sign security nor the decompression feature enabled. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?65 design security september 2012 altera corporation stratix iv device handbook volume 1 stratix iv security protection stratix iv device designs are protected from copying, reverse engineering, and tampering using configuration bitstream encryption. security against copying the security key is securely stored in th e stratix iv device and cannot be read out through any interfaces. in addition, as config uration file read-back is not supported in stratix iv devices, the design information cannot be copied. security against reverse engineering reverse engineering from an encrypted configuration file is very difficult and time consuming because the stratix iv configuration file form ats are proprietary and the file contains millions of bits which require specific decryption. reverse engineering the stratix iv device is just as difficult be cause the device is manufactured on the most advanced 40-nm process technology. security against tampering the non-volatile keys are one-time programma ble. after the tamper protection bit is set in the key programming file generated by the quartus ii software, the stratix iv device can only be configured with config uration files encrypted with the same key. aes decryption block the main purpose of the aes decryption block is to decrypt the configuration bitstream prior to entering data decompression or configuration. prior to receiving encrypted data, you must enter and store the 256-bit security key in the device. you can choose between a non-volati le security key and a volatile security key with battery backup. the security key is scrambled prior to storin g it in the key storage to make it more difficult for anyone to retrieve the stored key using de-capsulation of the device. flexible security key storage stratix iv devices support two types of security key programming?volatile and non-volatile keys. table 10?19 lists the differences between volatile keys and non-volatile keys. table 10?19. security key options (part 1 of 2) options volatile key non-volatile key key programmability reprogrammable and erasable one-time programmable external battery required not required key programming method (1) on-board on and off board 10?66 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices design security stratix iv device handbook september 2012 altera corporation volume 1 you can program the non-volatile key to th e stratix iv device without an external battery. also, there are no additional requ irements to any of the stratix iv power supply inputs. v ccbat is a dedicated power supply for volatile key storage and not shared with other on-chip power supplies, such as v ccio or v cc . v ccbat continuously supplies power to the volatile register regardless of the on-chip supply condition. 1 after power-up, you must wait 300 ms ( porsel = 0) or 12 ms ( porsel = 1) before beginning key programming to ensure that v ccbat is at full rail. 1 for more information about how to calculate the key retention time of the battery used for volatile key storage, refer to the stratix iii, stratix iv, stratix v, hardcopy iii and hardcopy iv powerplay early power estimator . f for more information about battery specifications, refer to the dc and switching characteristics for stratix iv devices chapter. f for more information about the v ccbat pin connection recommendations, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . stratix iv design security solution stratix iv devices are sram-based devices. to provide design security, stratix iv devices require a 256-bit security key for configuration bitstream encryption. you can carry out secure configuration in the following steps, as shown in figure 10?29 : 1. program the security key into the stratix iv device. 2. program the user-defined 256-bit aes keys to the stratix iv device through the jtag interface. 3. encrypt the configuration file and store it in the external memory. 4. encrypt the configuration file with the same 256-bit keys used to program the stratix iv device. encryption of the config uration file is done using the quartus ii software. the encrypted configuration file is then loaded into the external memory, such as a configuration or flash device. 5. configure the stratix iv device. design protection secure against copying and reverse engineering secure against copying and reverse engineering. tamper resistant if tamper protection bit is set. note to table 10?19 : (1) key programming is carried out using the jtag interface. table 10?19. security key options (part 2 of 2) options volatile key non-volatile key chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?67 design security september 2012 altera corporation stratix iv device handbook volume 1 at system power-up, the external memory device sends the encrypted configuration file to the stratix iv device. security modes available the following security modes are av ailable on the stratix iv device. volatile key secure operation with volatile key programmed and required external battery: this mode accepts both encrypted and unencr ypted configuration bitstreams. use the unencrypted configuration bitstream support for board-level testing only. non-volatile key secure operation with one time programma ble (otp) security key programmed: this mode accepts both encrypted and unencr ypted configuration bitstreams. use the unencrypted configuration bitstream support for board level testing only. non-volatile key with ta mper protection bit set secure operation in tamper resistant mode with otp security key programmed: only encrypted configuration bitstreams are allowed to configure the device. tamper protection disables jtag configuration with unencrypted configuration bitstream. figure 10?29. design security (note 1) note to figure 10?29 : (1) step 1, step 2, and step 3 correspond to the procedure described in ?design security? on page 10?63 . user-defined aes key key storage encrypted configuration file memory or configuration device stratix iv device aes decryption step 1 step 2 step 3 10?68 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices design security stratix iv device handbook september 2012 altera corporation volume 1 1 enabling the tamper protection bit disables test mode in stratix iv devices. this process is irreversible and prevents altera from conducting carry-out failure analysis if test mode is disabled. contact altera technical support to enable the tamper protection bit. no key operation only unencrypted configuration bitstreams are allowed to configure the device. table 10?20 lists the different security modes and configuration bitstream supported for each mode. supported configuration schemes the stratix iv device support s only selected configuration schemes, depending on the security mode you select when you encrypt the stratix iv device. figure 10?30 shows the restrictions of each secu rity mode when encrypting stratix iv devices. table 10?20. security modes supported mode (1) function configuration file volatile key secure encrypted board-level testing unencrypted non-volatile key secure encrypted board-level testing unencrypted non-volatile key with tamper protection bit set secure (tamper resistant) (2) encrypted notes to table 10?20 : (1) in no key operation, only the unencrypt ed configuration file is supported. (2) the tamper protection bit setting does not prevent the device from being reconfigured. figure 10?30. security modes in stratix iv devices?sequence and restrictions volatile key unencrypted or encrypted configuration file no key unencrypted configuration file non-volatile key unencrypted or encrypted configuration file non-volatile key with tamper-protection bit set encrypted configuration file chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?69 design security september 2012 altera corporation stratix iv device handbook volume 1 table 10?21 lists the configuration modes allowed in each of the security modes. you can use the design security feature wi th other configuration features, such as compression and remote system upgrade features. when you use compression with the design security feature, the configuration file is first compressed and then encrypted using the quartus ii software. duri ng configuration, th e stratix iv device first decrypts and then decompresses the configuration file. document revision history table 10?22 lists the revision history for this chapter. table 10?21. allowed configuration modes for various security modes (note 1) security mode configuration file allowed configuration modes no key unencrypted all configuration modes that do not engage the design security feature. secure with volatile key encrypted passive serial with aes (and/or with decompression) fast passive parallel with aes (and/or with decompression) remote update fast as with aes (and/or with decompression) fast as (and/or with decompression) board-level testing with volatile key unencrypted all configuration modes that do not engage the design security feature. secure with non-volatile key encrypted passive serial with aes (and/or with decompression) fast passive parallel with aes (and/or with decompression) remote update fast as with aes (and/or with decompression) fast as (and/or with decompression) board-level testing with non-volatile key unencrypted all configuration modes that do not engage the design security feature. secure in tamper resistant mode using non-volatile key with tamper protection set encrypted passive serial with aes (and/or with decompression) fast passive parallel with aes (and/or with decompression) remote update fast as with aes (and/or with decompression) fast as (and/or with decompression) note to table 10?21 : (1) there is no impact to the configuration time required when compared with unencrypted config uration modes excep t fpp with aes (and/or decompression), which requires a dclk that is 4 the data rate. table 10?22. document revision history (part 1 of 2) date version changes september 2012 3.5 updated the ?fpp configuration using a max ii device as an external host? section to close fb #36583 and #63157. updated the ?estimating active serial configuration time? section to close fb #64163. updated the ?ps configuration using a max ii device as an external host? section to close fb #63157. updated figure 10?1 , figure 10?2 , figure 10?3 , figure 10?10 , figure 10?11 and figure 10?12 to close fb #63155. december 2011 3.4 updated table 10?2 and table 10?7. 10?70 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices design security stratix iv device handbook september 2012 altera corporation volume 1 april 2011 3.3 updated the ?fpp configuration using a max ii device as an external host?, ?fast active serial configuration (serial configuration devices)?, and ?ps configuration using a max ii device as an external host?. updated table 10?10. february 2011 3.2 updated the ?fast active serial configurat ion (serial configuration devices)?, ?fpp configuration using a max ii device as an external host? ?configuration data decompression?, and ?user watchdog timer? sections. updated table 10?2, table 10?4, table 10?5, table 10?7, and table 10?9. applied new template. minor text edits. march 2010 3.1 added the ?guidelines for connecting serial configuration devices on an as interface? section. updated the ?power-on reset circuit? and ? fast active serial configuration (serial configuration devices)? sections. updated table 10?2, table 10?4, table 10?5, table 10?10, and table 10?13. updated figure 10?16 and figure 10?17 with note 5. updated figure 10?4, figure 10?5, and figure 10?13. updated the reference in the ?configuration schemes? section. november 2009 3.0 updated table 10?1 and table 10?2. updated the ?fpp configuration using a max ii device as an external host?,?fast active serial configuration (serial configuration devices)?, ?device configuration pins?, ?remote system upgrades?, ?remote system upgrade mode?, ?estimating active serial configuration time?, ?remote system u pgrade state machine?, and ?user watchdog timer? sections. removed table 10-4, table 10-7, table 10-8, and table 10-25. minor text edits. june 2009 2.3 updated the ?vccpd pins?, ?fpp configuration using a max ii device as an external host?, ?estimating active serial configuration time?, ?fast active serial configuration (serial configuration devices)?, ?remote s ystem upgrades?, ?ps configuration using a max ii device as an external host?, and ?ps configuration using a download cable? sections. updated table 10?3, table 10?13 and table 10?2. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. april 2009 2.2 updated table 10?2. march 2009 2.1 updated table 10?1, table 10?2, and table 10?9. removed ?referenced documents? section. november 2008 2.0 updated ?fast active serial configuration (serial configuration devices)? and ?jtag configuration? sections. updated figure 10?4, figure 10?5, figure 10?6, and figure 10?13. updated table 10?2 and table 10?13. may 2008 1.0 initial release. table 10?22. document revision history (part 2 of 2) date version changes siv51011-3.2 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 11. seu mitigation in stratix iv devices this chapter describes how to use the er ror detection cyclical redundancy check (crc) feature when a stratix ? iv device is in user mode and recovers from crc errors. the purpose of the error detection cr c feature in the stratix iv device is to detect a flip in any of the configuratio n random access memory (cram) bits in stratix iv devices due to a soft error. with the error detection circuitry, you can continuously verify the integrity of the configuration cram bits. in critical applications such as avionics , telecommunications, system control, and military applications, it is importan t to be able to do the following: confirm that the configuration data stor ed in a stratix iv device is correct alert the system to the occurrence of a configuration error 1 the error detection feature is enhanced in the stratix iv device family. similar to stratix iii devices, the error detection and recovery time for single-event upset (seu) in stratix iv devices is reduced when compared with stratix ii devices. f for more information about test methodology for enhanced error detection in stratix iv devices, refer to an 539: test methodology of error detection and recovery using crc in altera fpga devices . dedicated circuitry is built into stratix iv devices and consis ts of a crc error detection feature that optionally checks for seus continuously and automatically. 1 for stratix iv devices, the error detection crc feature is provided in the quartus ? ii software version 8.0 and onwards. using error detection crc for the stratix iv device family has no impact on fitting or performance of your device. this chapter contains the following sections: ?error detection fundamentals? on page 11?2 ?configuration error detection? on page 11?2 ?user mode error detection? on page 11?2 ?error detection pin description? on page 11?5 ?error detection block? on page 11?6 ?error detection timing? on page 11?8 ?recovering from crc errors? on page 11?11 february 2011 siv51011-3.2 11?2 chapter 11: seu mitigation in stratix iv devices error detection fundamentals stratix iv device handbook february 2011 altera corporation volume 1 error detection fundamentals error detection determines whether the data received is corrupted during transmission. to accomplish this, the tran smitter uses a function to calculate a checksum value for the data and appends the checksum to the original data frame. the receiver uses the same calculation methodology to generate a checksum for the received data frame and compares the received checksum to the transmitted checksum. if the two checksum values are equal, the received data frame is correct and no data corruption occurred during transmission or storage. the error detection crc feature uses the same concept. when stratix iv devices are configured successfully and ar e in user mode, the error detection crc feature ensures the integrity of the configuration data. 1 there are two crc error checks. one crc error check always runs during configuration and a second optional crc erro r check runs in the background in user mode. both crc error checks use the same crc polynomial but different error detection implementations. for more information, refer to the ?configuration error detection? and ?user mode error detection? sections. configuration error detection in configuration mode, a frame-based crc is stored within the configuration data and contains the crc value for each data frame. during configuration, the st ratix iv device calculates the crc value based on the frame of data that is received and compares it against the frame crc value in the data stream. configuration continues until either the device detects an error or configuration is completed. in stratix iv devices, the crc value is ca lculated during the configuration stage. a parallel crc engine generates 16 crc check bits per frame and then stores them in cram. the cram chain used for storing the crc check bits is 16 bits wide and its length is equal to the number of frames in the device. user mode error detection stratix iv devices have built-in error detect ion circuitry to detect data corruption by soft errors in the cram cells. this feature allows all cram contents to be read and verified to match a configuration-computed crc value. soft errors are changes in a cram bit state due to an ionizing particle. the error detection capability continuous ly computes the crc of the configured cram bits and compares it with the pre-calc ulated crc. if the crcs match, there is no error in the current configuration cram bits. the process of error detection continues until the device is reset (by setting nconfig low). if you enable the crc error detection option in the quartus ii software, after the device transitions into user mode, the error detection process is enabled. the internal 100 mhz configuration oscillator is divided do wn by a factor of two to 256 (at powers of two) to be used as the clock source during the error detection process. you must set the clock divide factor in the quartus ii software. chapter 11: seu mitigation in stratix iv devices 11?3 user mode error detection february 2011 altera corporation stratix iv device handbook volume 1 a single 16-bit crc calculation is done on a per-frame basis. after it has finished the crc calculation for a frame, the resulting 16-bit signature is hex 0000 if there are no cram bit errors detected in a frame by th e error detection circuitry and the output signal crc_error is 0 . if a cram bit error is detected by the circuitry within a frame in the device, the resulting signature is non-zero. this causes the crc engine to start searching for the error bit location. error detection in stratix iv devices calc ulates crc check bits for each frame and pulls the crc_error pin high when it detects bit errors in the chip. within a frame, it can detect all single-bit, double-bit, and three-bit errors. the probability of more than three cram bits being flipped by an seu event is very low. in general, for all error patterns the probability of detection is 99.998%. the crc engine reports the bit location an d determines the type of error for all single-bit errors and over 99.641% of double-adjacent errors. the probability of other error patterns is very low and report of the location of bit flips is not guaranteed by the crc engine. you can also read-out the error bit location through the jtag and the core interface. shift these bits out through either the shift_ederror_reg jtag instruction or the core interface before the crc detects the next error in another frame. if the next frame also has an error, you must shift these bits out within the amount of time of one frame crc verification. you can choose to extend this time interval by slowing down the error detection clock frequency, but this slows down the error recovery time for the seu event. for the minimum update interv al for stratix iv devices, refer to table 11?6 on page 11?9 . if these bits are not shifted out before the next error location is found, the previous error location and error message is overwritten by the new information. the crc circuit continues to run, and if an erro r is detected, you must decide whether to complete a reconfiguration or to ignore the crc error. the error detection logic continues to calculate the crc_error and 16-bit signatures for the next frame of data regardless if any error has occurred in the current frame or not. you need to monitor these signals and take the appropriate actions if a soft error occurs. the error detection circuitry in stratix iv devices uses a 16-bit crc-ansi standard (16-bit polynomial) as the crc generator. the computed 16-bit crc signature for each fr ame is stored in the registers within the core. the total storage register size is 16 (t he number of bits per frame) the number of frames. the stratix iv device error detection feature does not check memory blocks and i/o buffers. thus, the crc_error signal might stay solid high or low depending on the error status of the previously checked cram frame. the i/o buffers are not verified during error detection because these bits us e flipflops as storage elements that are more resistant to soft errors when compared with cram cells. the support parity bits of mlab, m9k, and m144k are used to chec k the contents of the memory blocks for any errors. the m144k trimatrix memory bloc k has a built-in error correction code block that checks and corrects the errors in the block. f for more information, refer to the trimatrix embedded memory blocks in stratix iv devices chapter . 11?4 chapter 11: seu mitigation in stratix iv devices user mode error detection stratix iv device handbook february 2011 altera corporation volume 1 a jtag instruction, ederror_inject , is provided to test th e capability of the error detection block. this instruction is able to change the content of the 21-bit jtag fault injection register that is used for error injection in stratix iv devices, enabling the testing of the error detection block. 1 you can only execute the ederror_inject jtag instruction when the device is in user mode. table 11?1 lists the description of the ederror_inject jtag instruction. you can create a jam? file ( .jam ) to automate the testing and verification process. this allows you to verify the crc functionality in-system, on-the-fly, without having to reconfigure the device. you can then switch to the crc circuit to check for real errors induced by an seu. you can introduce a single-error or double -errors adjacent to each other to the configuration memory. this provides an extra way to facilitate design verification and system fault tolerance characterization. use the jtag fault injection register with the ederror_inject instruction to flip the readback bi ts. the stratix iv device is then forced into error test mode. the content of the jtag fault injection register is not loaded into the fault injection register during the processing of the last and first frame. it is only loaded at the end of this period. 1 you can only introduce error injection in th e first data frame, but you can monitor the error information at any time. for more information about the jtag fault injection register and fault injection register, refer to ?error detection registers? on page 11?7 . table 11?2 lists how the fault injection register is implemented and describes error injection. table 11?1. ederror_inject jtag instruction jtag instruction instruction code description ederror_inject 00 0001 0101 this instruction controls the 21-bit jtag fault injection register, which is used for error injection. table 11?2. fault injection register bit bit[20..19] bit[18..8] bit[7..0] description error type byte location of the injected error error byte value content error type (1) error injection type depicts the location of the injected error in the first data frame. depicts the location of the bit error and corresponds to the error injection type selection. bit[20] bit[19] 0 1 single-byte error injection 1 0 double-adjacent byte error injection 0 0 no error injection note to table 11?2 : (1) bit[20] and bit[19] cannot both be set to 1 as this is not a valid selection. the error detection circ uitry decodes this as no error injection. chapter 11: seu mitigation in stratix iv devices 11?5 error detection pin description february 2011 altera corporation stratix iv device handbook volume 1 1 after the test completes, altera recommends reconfiguring the device. automated single-event upset detection stratix iv devices offer on-chip circuitry for automated checking of seu detection. some applications that require the device to operate error-free in high-neutron flux environments require periodic checks to ensure continued data integrity. the error detection crc feature ensures data reliabil ity and is one of the best options for mitigating seu. you can implement the error detection cr c feature with existing circuitry in stratix iv devices, eliminating the need for external logic. the crc_error pin reports a soft error when the configuration cram data is corrupted. you must decide whether to reconfigure the device or to ignore the error. error detection pin description depending on the type of error detection feature you choose, you must use different error detection pins to monitor the data during user mode. crc_error pin table 11?3 describes the crc_error pin. 1 the wysiwyg function performs optimiza tion on the verilog quartus mapping (vqm) netlist within the quartus ii software. f for more information about the stratixiv_crcblock wysiwyg function, refer to the an 539: test methodology of error detect ion and recovery using crc in altera fpga devices . f for more information about the crc_error pin for stratix iv devices, refer to device pin-outs on the altera website. table 11?3. crc_error pin description pin name pin type description crc_error i/o and open-drain active-high signal indicates that the error detection circuit has detected errors in the configuration cram bits. this pin is optional and is used when the error detection crc circuit is enabled. when the error detection crc circuit is disabled, it is a user i/o pin. to use the crc_error pin, you can either tie this pin to v ccpgm through a 10k ?? resistor or, depending on the input voltage specification of the system receiving the signal, you can tie this pin to a different pull-up voltage. 11?6 chapter 11: seu mitigation in stratix iv devices error detection block stratix iv device handbook february 2011 altera corporation volume 1 error detection block you can enable the stratix iv device error detection block in the quartus ii software (refer to ?software support? on page 11?10 ). this block contains the logic necessary to calculate the 16-bit crc signature for the configuration cram bits in the device. the crc circuit continues running even if an error occurs. when a soft error occurs, the device sets the crc_error pin high. two types of crc detection checks the configuration bits: cram error checking ability (16-bit crc), which occurs during user mode to be used by the crc_error pin. for each frame of data, the pre-calculated 16-bit crc enters the crc circuit at the end of the frame data and determines whether there is an error or not. if an error occurs, the search engine starts to find the location of the error. the error messages are shifted out through the jtag instruction or core interface logics while the error detection block continues running. the jtag interface reads out the 16-bit crc result for the first frame and also shifts the 16-bit crc bits to the 16-bit crc storage registers for test purposes. single error, double errors, or double-errors adjacent to each other are deliberately introduced to configuration memory for testing and design verification. 16-bit crc that is embedded in every configuration data frame. during configuration, after a frame of data is loaded into the stratix iv device, the pre-computed crc is shifted into the crc circuitry. at the same time, the crc value for the da ta frame shifted-in is calculated. if the pre-computed crc and calculat ed crc values do not match, nstatus is set low. every data frame has a 16-bit crc; therefore, there are many 16-bit crc values for the whole configuration bi tstream. every device has different lengths of configuration data frame. 1 the ?error detection block? section describes the 16-bit crc only when the device is in user mode. chapter 11: seu mitigation in stratix iv devices 11?7 error detection block february 2011 altera corporation stratix iv device handbook volume 1 error detection registers there is one set of 16-bit registers in the error detection circuitry that stores the computed crc signature. a non-zero value on the syndrome register causes the crc_error pin to be set high. figure 11?1 shows the error detection circuitry, syndrome registers, and error injection block. table 11?4 lists the registers shown in figure 11?1 . figure 11?1. error detection block diagram error detection state machine fault injection register jtag fault injection register error injection block control signals 16-bit crc calculation and error search engine readback bit stream with expected crc included syndrome register 8 16 crc_error jtag update register user update register error message register 46 30 jtag shift register user shift register general routing jtag tdo table 11?4. error detection registers (part 1 of 2) register description syndrome register this register contains the crc signature of the current frame through the error detection verification cycle. the crc_error signal is derived from the contents of this register. error message register this 46-bit register contains information on the error type, location of the error, and the actual syndrome. the types of errors and location reported are single- and double-adjacent bit errors. the location bits for other types of errors are not identified by the error message register. the content of the register can be shifted out through the shift_ederror_reg jtag instruction or to the core through the core interface. 11?8 chapter 11: seu mitigation in stratix iv devices error detection timing stratix iv device handbook february 2011 altera corporation volume 1 error detection timing when you enable the crc feature through the quartus ii software, the device automatically activates the crc process after entering user mode, after configuration, and after initialization is complete. if an error is detected within a frame, crc_error is driven high at the end of the error location search, after the error message registe r is updated. at the end of this cycle, the crc_error pin is pulled low for a minimum of 32 clock cycles. if the next frame contains an error, crc_error is driven high again after the error message register is overwritten by the new value. you can start to unload the error message on each rising edge of the crc_error pin. error detection runs until the device is reset. the error detection circuitry runs off an inte rnal configuration osci llator with a divisor that sets the maximum frequency. table 11?5 lists the minimum and maximum error detection frequencies based on the best pe rformance of the internal configuration oscillator. jtag update register this register is automatically updated with the contents of the error message register one cycle after the 46-bit register content is validated. it includes a clock enable that must be asserted prior to being sampled into the jtag shift register. this requirement ensures that the jtag update register is not being written into by the contents of the error message register at the same time that the jtag shift register is reading its contents. user update register this register is automatically updated with the contents of the error message register, one cycle after the 46-bit register content is validated. it includes a clock enable that must be asserted prior to being sampled into the user shift register. this requirement ensures that the user update register is not being written into by the contents of the error message register at exactly the same time that the user shift register is reading its contents. jtag shift register this register is accessible by the jtag interface and allows the contents of the jtag update register to be sampled and read by the jtag instruction shift_ederror_reg . user shift register this register is accessible by the core logic and allows the contents of the user update register to be sampled and read by user logic. jtag fault injection register this 21-bit register is fully controlled by the jtag instruction ederror_inject . this register holds the information of the error injection that you want in the bitstream. fault injection register the content of the jtag fault injection register is loaded into this 21-bit register when it is being updated. table 11?4. error detection registers (part 2 of 2) register description table 11?5. minimum and maximum error detection frequencies device type error detection frequency maximum error detection frequency minimum error detection frequency valid divisors (n) stratix iv 100 mhz / 2 n 50 mhz 390 khz 1, 2, 3, 4, 5, 6, 7, 8 chapter 11: seu mitigation in stratix iv devices 11?9 error detection timing february 2011 altera corporation stratix iv device handbook volume 1 you can set a lower clock frequency by specifying a division factor in the quartus ii software (refer to ?software support? on page 11?10 ). the divisor is a power of two, in which n is between 1 and 8. the divisor ranges from 2 through 256. refer to equation 11?1 . 1 the error detection frequency reflects the frequency of the error detection process for a frame because the crc calculation in the stratix iv device is done on a per-frame basis. you must monitor the error message to avoid missing information in the error message register. the error message register is updated whenever an error occurs. the minimum interval time between each update for the error message register depends on the device and the error detection clock frequency. table 11?6 lists the estimated minimum interval time between each update for the error message register for stratix iv devices. crc calculation time for the error detection circuitry to check from the first until the last frame depends on the device and the error detection clock frequency. equation 11?1. error detection frequency 100 mhz 2 n ----------------------- - = table 11?6. minimum update interval for error message register (1) device timing interval ( ? s) ep4sgx70 13.8 ep4sgx110 13.8 ep4sgx180 19.8 ep4sgx230 19.8 ep4sgx290 21.8 ep4sgx360 21.8 ep4sgx530 26.8 ep4se230 19.8 ep4se360 21.8 ep4se530 26.8 ep4se820 33.8 ep4s40g2 19.8 ep4s40g5 26.8 ep4s100g2 19.8 ep4s100g3 26.8 ep4s100g4 26.8 ep4s100g5 26.8 note to table 11?6 : (1) these timing numbers are preliminary. 11?10 chapter 11: seu mitigation in stratix iv devices error detection timing stratix iv device handbook february 2011 altera corporation volume 1 table 11?7 lists the estimated time for each crc calculation with minimum and maximum clock frequencies for stratix iv devices. the minimum crc calculation time is calculated by using the maximum error detection frequency with a divisor factor of one, and the maximum crc calculat ion time is calculated by using the minimum error detection frequency with a divisor factor of eight. software support the quartus ii software version 8.0 and onwards supports the error detection crc feature for stratix iv devices. enabling this feature generates the crc_error output to the optional dual purpose crc_error pin. the error detection crc feature is controlled by the device and pin options dialog box in the quartus ii software. to enable the error detection feature using crc, follow these steps: 1. open the quartus ii software and load a project using a stratix iv device. 2. on the assignments menu, click settings . the settings dialog box is shown. 3. in the category list, select device . the device page is shown. 4. click device and pin options . the device and pin options dialog box is shown (refer to figure 11?2 ). table 11?7. crc calculation time (1) device minimum time (ms) maximum time (s) ep4sgx70 111 30.90 ep4sgx110 111 30.90 ep4sgx180 225 62.44 ep4sgx230 225 62.44 ep4sgx290 296 82.05 ep4sgx360 296 82.05 ep4sgx530 398 110.38 ep4se230 225 62.44 ep4se360 296 82.05 ep4se530 398 110.38 ep4se820 577 160.00 ep4s40g2 225 62.44 ep4s40g5 398 110.38 ep4s100g2 225 62.44 ep4s100g3 398 110.38 ep4s100g4 398 110.38 ep4s100g5 398 110.38 note to table 11?7 : (1) these timing numbers are preliminary. chapter 11: seu mitigation in stratix iv devices 11?11 recovering from crc errors february 2011 altera corporation stratix iv device handbook volume 1 5. in the device and pin options dialog box, click the error detection crc tab. 6. turn on enable error detection crc ( figure 11?2 ). 7. in the divide error check frequency by pull-down list, enter a valid divisor as listed in table 11?5 on page 11?8 . 1 the divide value divides the frequency of the configuration osci llator output clock that clocks the crc circuitry. 8. click ok . recovering from crc errors the system that the stratix iv device resi des in must control device reconfiguration. after detecting an error on the crc_error pin, strobing the nconfig signal low directs the system to perform the reconfiguration at a time when it is safe for the system to reconfigure the device. when the data bit is rewritten with the co rrect value by reconfiguring the device, the device functions correctly. while soft errors are uncommon in altera devi ces, certain high-reliability applications require a design to account for these errors. figure 11?2. enabling the error detection crc feature in the quartus ii software 11?12 chapter 11: seu mitigation in stratix iv devices recovering from crc errors stratix iv device handbook february 2011 altera corporation volume 1 document revision history table 11?8 lists the revision history for this chapter. table 11?8. document revision history date version changes february 2011 3.2 applied new template. minor text edits. march 2010 3.1 updated table 11?3 and table 11?6. minor text edits. november 2009 3.0 updated table 11?3, table 11?5, table 11?6, and table 11?7. updated the ?crc_error pin? section. minor text edits. june 2009 2.3 added an introductory paragraph to increase search ability. removed the conclusion section. minor text edits. april 2009 2.2 updated table 11?6 and table 11?7. march 2009 2.1 updated ?error detection timing? section. updated table 11?6. added table 11?7. removed ?critical error detection?, ?critical error pin?, and ?referenced documents? sections. november 2008 2.0 minor text edits. may 2008 1.0 initial release. siv51012-3.2 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 12. jtag boundary-scan testing in stratix iv devices the ieee std. 1149.1 boundary-scan test (bst) circuitry available in stratix ? iv devices provides a cost-effective and efficien t way to test systems that contain devices with tight lead spacing. circuit boards with altera and other ieee std. 1149.1-compliant devices can use extest , sample/preload , and bypass modes to create serial patterns that internally test the pin co nnections between devices and check device operation. this chapter describes how to use the ieee std. 1149.1 bst circuitry in stratix iv devices. the features are simila r to stratix iii devices, unless stated otherwise in this chapter. this chapter contains the following sections: ?bst architecture? ?bst operation control? on page 12?2 ?i/o voltage support in a jtag chain? on page 12?4 ?bst circuitry? on page 12?4 ?bsdl support? on page 12?4 bst architecture a device operating in ieee std. 1149.1 bst mode uses four required pins, tdi , tdo , tms, tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have internal weak pull-up resistors. the tdo output pin and all the jtag input pins are powered by the 2.5-v/3.0-v v ccpd supply of i/o bank 1a. all user i/o pins are tri-stated during jtag configuration. f for more information about the descriptio n and functionality of all jtag pins, registers used by the ieee std. 1149.1 bst circuitry, and the test access port (tap) controller, refer to the ieee 1149.1 (jtag) boundary-sca n testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook . february 2011 siv51012-3.2 12?2 chapter 12: jtag boundary-scan testing in stratix iv devices bst operation control stratix iv device handbook february 2011 altera corporation volume 1 bst operation control table 12?1 lists the boundary-scan register length for stratix iv devices. table 12?2 lists the idcode information for stratix iv devices. table 12?1. boundary-scan register length in stratix iv devices device boundary-scan register length ep4sgx70 1506 ep4sgx110 1506 ep4sgx180 2274 ep4sgx230 2274 ep4sgx290 (1) 2682 ep4sgx360 (1) 2682 ep4sgx530 2970 ep4se230 2274 ep4se360 2682 ep4se530 2970 ep4se820 3402 ep4s40g2 2274 ep4s40g5 2970 ep4s100g2 2274 ep4s100g3 2970 ep4s100g4 2970 ep4s100g5 2970 note to table 12?1 : (1) for the f1932 package of ep4sgx 290 and ep4sgx360 devices , the boundary-scan regi ster length is 2970. table 12?2. idcode information for stratix iv devices (part 1 of 2) device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep4sgx70 0000 0010 0100 0010 0000 000 0110 1110 1 ep4sgx110 0000 0010 0100 0000 0000 000 0110 1110 1 ep4sgx180 0000 0010 0100 0010 0001 000 0110 1110 1 ep4sgx230 0000 0010 0100 0000 1001 000 0110 1110 1 ep4sgx290 (3) 0000 0010 0100 0010 0010 000 0110 1110 1 ep4sgx290 (4) 0000 0010 0100 0100 0011 000 0110 1110 1 ep4sgx360 (3) 0000 0010 0100 0000 0010 000 0110 1110 1 ep4sgx360 (4) 0000 0010 0100 1000 0011 000 0110 1110 1 ep4sgx530 0000 0010 0100 0000 0011 000 0110 1110 1 ep4se230 0000 0010 0100 0001 0001 000 0110 1110 1 ep4se360 0000 0010 0100 0001 0010 000 0110 1110 1 chapter 12: jtag boundary-scan testing in stratix iv devices 12?3 bst operation control february 2011 altera corporation stratix iv device handbook volume 1 1 if the device is in reset state, when the nconfig or nstatus signal is low, the device idcode might not be read correctly. to read the device idcode correctly, you must issue the idcode jtag instruction only when the nstatus signal is high. f for more information about the following topics, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook : jtag instruction codes with descriptions tap controller state-machine timing requirements for ieee std. 1149.1 signals instruction mode mandatory jtag instructions ( sample/preload , extest, and bypass ) optional jtag instructions ( idcode , usercode , clamp, and highz ) ep4se530 0000 0010 0100 0001 0011 000 0110 1110 1 ep4se820 0000 0010 0100 0000 0100 000 0110 1110 1 ep4s40g2 (5) 0000 0010 0100 0100 0001 000 0110 1110 1 ep4s40g5 (6) 0000 0010 0100 0010 0011 000 0110 1110 1 ep4s100g2 (5) 0000 0010 0100 0100 0001 000 0110 1110 1 ep4s100g3 0000 0010 0100 1010 0011 000 0110 1110 1 ep4s100g4 0000 0010 0100 0110 0011 000 0110 1110 1 ep4s100g5 (6) 0000 0010 0100 0010 0011 000 0110 1110 1 notes to table 12?2 : (1) the msb is on the left. (2) the lsb of the idcode is always 1. (3) the idcode is applicable for all packages except f1932. (4) the idcode is applicable for package f1932 only. (5) for the es1 device, the idcode is the same as the idcode of ep4sgx230. (6) for the es1 device, the idcode is the same as the idcode of ep4sgx530. table 12?2. idcode information for stratix iv devices (part 2 of 2) device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) 12?4 chapter 12: jtag boundary-scan testing in stratix iv devices i/o voltage support in a jtag chain stratix iv device handbook february 2011 altera corporation volume 1 i/o voltage support in a jtag chain the jtag chain supports several devices. ho wever, you must use caution if the chain contains devices that have different v ccio levels. f for more information, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook . bst circuitry the ieee std. 1149.1 bst circuitry is enable d after device power-up. you can perform bst on stratix iv devices before, during, an d after configuration. stratix iv devices support bypass , idcode , and sample jtag instructions during configuration without interrupting configuration. to send all ot her jtag instructions, you must interrupt configuration using the config_io jtag instruction. f for more information, refer to an 39: ieee std. 1149.1 (jta g) boundary-scan testing in altera devices . f for more information about using the config_io jtag instruction for dynamic i/o buffer configuration, considerations when performing bst for configured devices, and jtag pin connections to mask-out the bst circuitry, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook . f for more information about using the ieee std.1149.1 circuitry for device configuration, refer to the configuration, design security , remote system upgrades in stratix iv devices chapter. f if you must perform bst for configured devi ces, you must use the quartus ii software version 8.1 and onwards to generate the design-specific boundary-scan description language (bsdl) files. for the procedure to generate post-configured bsdl files using the quartus ii software, refer to the bsdl files generation in quartus ii on the altera website. bsdl support bsdl, a subset of vhdl, provides a syntax th at allows you to describe the features of an ieee std. 1149.1 bst-capable device that can be tested. f for more information about bsdl files for ieee std. 1149.1-compliant stratix iv devices, refer to the stratix iv bsdl files on the altera website. f bsdl files for ieee std. 1149.1-compliant stratix iv devices can also be generated using the quartus ii software version 8.1 and onwards. for more information about the procedure to generate bsdl files using the quartus ii software, refer to the bsdl files generation in quartus ii on the altera website. chapter 12: jtag boundary-scan testing in stratix iv devices 12?5 bsdl support february 2011 altera corporation stratix iv device handbook volume 1 document revision history table 12?3 lists the revision history for this chapter. table 12?3. document revision history date version changes february 2011 3.2 applied new template. minor text edits. march 2010 3.1 updated the hand note in the ?bst operation control? section. changed ?idcode jtag instruction? to read ?idcode? as needed. minor text edits november 2009 3.0 updated table 12?1 and table 12?2. minor text edits. june 2009 2.3 added an introductory paragraph to increase search ability. removed the conclusion section. minor text edits. april 2009 2.2 updated table 12?1. march 2009 2.1 updated table 12?1 and table 12?2. removed ?referenced documents? section. november 2008 2.0 minor text edits. april 2010 1.0 initial release. 12?6 chapter 12: jtag boundary-scan testing in stratix iv devices bsdl support stratix iv device handbook february 2011 altera corporation volume 1 siv51013-3.2 ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 february 2011 feedback subscribe iso 9001:2008 registered 13. power management in stratix iv devices this chapter describes power management in stratix ? iv devices. stratix iv devices offer programmable power technology options for low-power operation. you can use these options, along with speed grade choice s, in different permutations to give the best power and performance combination. for thermal management, use the stratix iv internal temperature sensing device (tsd) with built-in analog-to-digital converter (adc) circuitry or external tsd with an external temperature sensor to easily incorporate this feature in your designs. being able to monitor the junction temperature of the device at any time also of fers the ability to control air flow to the device and save power for the whole system. overview stratix iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allo wing you to innovate without compromise. stratix iv devices use advanced power ma nagement techniques to enable both density and performance increases while simultaneously reducing power dissipation. the total power of an fpga includes static and dynamic power. static power is the power consumed by the fpga when it is configured but no clocks are operating. dynamic power is the switching power when the device is configured and running. you configure dynamic powe r with the equation shown in equation 13?1 . equation 13?1 shows that frequency is design dependant. however, you can vary the voltage to lower dynamic power consumptio n by the square value of the voltage difference. stratix iv devices minimize st atic and dynamic power with advanced process optimizations and programmable power technology. these technologies enable stratix iv designs to optimally meet design-specific performance requirements with the lowest possible power. the quartus ? ii software optimizes all designs wi th stratix iv power technology to ensure performance is met at the lowest power consumption. this automatic process allows you to concentrate on the function ality of the design instead of the power consumption of the design. equation 13?1. dynamic power equation (1) note to equation 13?1 : (1) p = power; c = load capacitan ce; and v = supply voltage level. p 1 2 -- - cv 2 frequency ? = february 2011 siv51013-3.2 13?2 chapter 13: power management in stratix iv devices stratix iv power technology stratix iv device handbook february 2011 altera corporation volume 1 power consumption also affects thermal ma nagement. stratix iv devices offer a tsd feature that self-monitors the device junc tion temperature and can be used with external circuitry for other ac tivities, such as controllin g air flow to the stratix iv fpga. this chapter contains the following sections: ?stratix iv power technology? ?stratix iv external po wer supply requirements? ?temperature sensing diode? stratix iv power technology the following sections describe stra tix iv programmable power technology. programmable power technology stratix iv devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operat ion performed by the quartus ii software without user intervention. setting a tile to high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies brought into the stratix iv device. in a de sign compilation, the quartus ii software determines whether a tile must be in high-speed or low-power mode based on the timing constraints of the design. f for more information about how the quartu s ii software uses programmable power technology when compiling a design, refer to an 514: power optimization in stratix iv fpgas . a stratix iv tile can consist of the following: memory logic array block (mlab)/logic array block (lab) pairs with routing to the pair mlab/lab pairs with routing to the pair and to adjacent digital signal processing (dsp)/memory block routing trimatrix memory blocks dsp blocks all blocks and routing associated with the tile share the same setting of either high-speed or low-power mode. by default, tiles that include dsp blocks or memory blocks are set to high-speed mode for op timum performance. unused dsp blocks and memory blocks are set to low-power mode to minimize static power. clock networks do not support programmable power technology. with programmable power technology, fast er speed grade fpgas may require less power because there are fewer high-speed mlab and lab pairs, when compared with slower speed grade fpgas. the slow er speed grade device may have to use more high-speed mlab and lab pairs to meet performance requirements, while the faster speed grade device can meet performance requirements with mlab and lab pairs in low-power mode. chapter 13: power management in stratix iv devices 13?3 stratix iv external power supply requirements february 2011 altera corporation stratix iv device handbook volume 1 the quartus ii software sets unused devi ce resources in the design to low-power mode to reduce static and dynamic power. it also sets the following resources to low-power mode when they are not used in the design: labs and mlabs trimatrix memory blocks dsp blocks if a phase-locked loop (pll) is inst antiated in the design, asserting the areset pin high keeps the pll in low-power mode. table 13?1 lists the available stratix iv progra mmable power capabilities. speed grade considerations can add to the permutations to give you flexibility in designing your system. stratix iv external po wer supply requirements this section describes the different external power supplies required to power stratix iv devices. you can supply some of the power supply pins with the same external power supply, provided they have the same voltage level. f for power supply pin connection guidelines and power regulator sharing, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . f for each altera recommended power supply?s operating conditions, refer to the dc and switching characteristic s for stratix iv devices chapter. table 13?1. programmable power capabilities in stratix iv devices feature programmable power technology lab yes routing yes memory blocks fixed setting (1) dsp blocks fixed setting (1) global clock networks no note to table 13?1 : (1) tiles with dsp blocks and memory bl ocks that are used in th e design are always set to high-speed mode. by default, unused dsp blocks and memo ry blocks are set to low-power mode. 13?4 chapter 13: power management in stratix iv devices temperature sensing diode stratix iv device handbook february 2011 altera corporation volume 1 temperature sensing diode the stratix iv tsd uses the characteristics of a pn junction diode to determine die temperature. knowing the junction temperature is crucial for thermal management. historically, junction temperature is calcul ated using ambient or case temperature, junction-to-ambient (ja) or ju nction to-case (jc) thermal resistance, and device power consumption. stratix iv devices can either monitor its die temperature with the internal tsd with built-in adc circuitry or the external tsd with an external temperature sensor. this allows you to control the air flow to the device. you can use the stratix iv internal tsd in two different modes of operation? power-up mode and user mode. for power-up mode, the internal tsd reads the die?s temperature during configuration if the alttemp_sense megafunction is enabled in your design. the alttemp_sense mega function allows temperature sensing during device user mode by asserting the clken signal to the internal tsd circuitry. to reduce device static power, disable the inte rnal tsd with built-in adc circuitry when not in use. f for more information about using the alttemp_sense megafunction, refer to the thermal sensor (alttemp_sense) megafunction user guide . the external temperature sensor steers bi as current through the stratix iv external tsd, which measures forward voltage and converts this reading to temperature in the form of an 8-bit signed number (7 bits pl us sign). the 8-bit output represents the junction temperature of the stratix iv device and can be used for intelligent power management. external pin connections the stratix iv external tsd requires two pins for voltage reference. figure 13?1 shows how to connect the external tsd with an ex ternal temperature sensor device. as an example, external temperature sensing devices, such as max1619, max1617a, max6627, and adt 7411, can be connected to the two external tsd pins for temperature reading. f for more information about the external tsd specification, refer to the dc and switching characteristics for stratix iv devices chapter. figure 13?1. tsd external pin connections in stratix iv devices stratix i v de v ice tempdiodep external tsd tempdiode n external temperat u re sensor chapter 13: power management in stratix iv devices 13?5 temperature sensing diode february 2011 altera corporation stratix iv device handbook volume 1 the tsd is a very sensitive circuit that can be influenced by noise coupled from other traces on the board and possib ly within the device package itself, depending on your device usage. the interfacing device registers? temperature is based on millivolts (mv) of difference, as seen at the extern al tsd pins. switching the i/o near the tsd pins can affect the temperature reading. altera recommends taking temperature readings during periods of inactivity in the device or use the internal tsd with built-in adc circuitry. the following are board connection guidelines for the tsd external pin connections: the maximum trace lengths for the tempdiode p /tempdiode n traces must be less than eight inches. route both traces in parallel and place them close to each other with grounded guard tracks on each side. altera recommends 10-mils width and space for both traces. route traces through a minimum number of vias and crossunders to minimize the thermocouple effects. ensure that the number of vias are the same on both traces. ensure both traces are approximately the same length. avoid coupling with toggling signals (for example, clocks and i/o) by having the gnd plane between the diode traces and the high frequency signals. for high-frequency noise filtering, place an external capacitor (close to the external chip) between the tempdiode p /tempdiode n trace. for maxim devices, use an external capacitor between 2200 pf to 3300 pf. place a 0.1 uf bypass capacitor close to the external device. you can use internal tsd with built-in adc circuitry and external tsd at the same time. if you only use internal adc circuitry, the external tsd pins (tempdiode p /tempdiode n ) can connect these pins to gnd because the external tsd pins are not used. f for more information about the tempdiode p /tempdiode n pin connection when you are not using an external tsd, refer to the stratix iv gx and stratix iv e pin connection guidelines . f for device specification and connection guidelines, refer to the external temperature sensor device data sheet from the device manufacturer. 13?6 chapter 13: power management in stratix iv devices temperature sensing diode stratix iv device handbook february 2011 altera corporation volume 1 document revision history table 13?2 lists the revision history for this chapter. table 13?2. document revision history date version changes february 2011 3.2 applied new template. minor text edits. march 2010 3.1 updated the ?external pin connections? section. minor text edits. november 2009 3.0 updated the ?temperature sensing diode? and ?external pin connections? sections. updated equation 13?1. removed table 13-2: stratix iv external power supply pins. minor text edits. june 2009 2.2 updated the ?external pin connections? section. added an introductory paragraph to increase search ability. removed the conclusion section. march 2009 2.1 updated ?temperature sensing diode? and ?external pin connections? sections. updated figure 13?1. removed ?referenced documents? section. november 2008 2.0 minor text edits. may 2008 1.0 initial release. september 2012 altera corporation stratix iv device handbook volume 1 additional information about this handbook this chapter provides additional info rmation about the document and altera. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature nontechnical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, info?2 additional information typographic conventions stratix iv device handbook september 2012 altera corporation volume 1 courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. h the question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. m the multimedia icon directs you to a related multimedia presentation. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. the feedback icon allows you to submit feedback to altera about the document. methods for collecting feedback vary as appropriate for each document. the social media icons allow you to inform others about altera documents. methods for submitting information vary as appropriate for each medium. visual cue meaning |
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